am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 68

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

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maintained until IOR goes inactive, at which time the
access cycle ends. Data is removed from SD0-7 within
30 ns.
The PCnet-ISA
cle operation for all resources (registers, PROMs,
SRAM) if SBHE has been left unconnected, such as in
the case of an 8-bit system like the PC/XT.
Ethernet Controller Register Cycles
Ethernet controller registers (RAP, RDP, ISACSR) are
naturally 16-bit resources but can be configured to oper-
ate with 8-bit bus cycles provided the proper protocol is
followed. This is programmable by the EEPROM. This
means on a read, the PCnet-ISA
drive the low byte of the system data bus; if an odd byte
is accessed, it will be swapped down. The high byte of
the system data bus is never driven by the PCnet-ISA
controller under these conditions. On a write, the even
byte is placed in a holding register. An odd-byte write is
internally swapped up and augmented with the even
byte in the holding register to provide an internal 16-bit
write. This allows the use of 8-bit I/O bus cycles which
are more likely to be compatible with all clones, but re-
quires that both bytes be written in immediate
succession. This is accomplished simply by treating the
PCnet-ISA
ware resources. The motherboard will convert the 16-bit
accesses done by software into two sequential 8-bit ac-
cesses, an even- byte access followed immediately by
an odd-byte access.
An access cycle begins with the Permanent Master driv-
ing AEN LOW, driving the address valid, and driving IOR
or IOW active. The PCnet-ISA
combination of signals and drives IOCHRDY LOW.
IOCS16 will also be driven LOW if 16-bit I/O bus cycles
are enabled. When the register data is ready, IOCHRDY
will be released HIGH. This condition is maintained until
IOR or IOW goes inactive, at which time the bus cycle
ends.
The PCnet-ISA
cle operation for all resources (registers, PROMs,
SRAM) if SBHE has been left unconnected, such as in
the case of an 8-bit system like the PC/XT.
RESET Cycles
A read to the reset address causes an PCnet-ISA
troller reset. This has the same effect as asserting the
RESET pin on the PCnet-ISA
pens during a system power-up or hard boot. The
subsequent write cycle needed in the NE2100 LANCE-
based family of Ethernet cards is not required but does
not have any harmful effects. IOCS16 is not asserted in
this cycle.
AMD
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controller controller registers as 16-bit soft-
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controller will perform 8-bit ISA bus cy-
controller will perform 8-bit ISA bus cy-
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controller, such as hap-
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controller detects this
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controller will only
P R E L I M I N A R Y
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con-
Am79C961
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ISA Configuration Register Cycles
The ISA configuration register is accessed by placing
the address of the desired register into the RAP and
reading the IDP. The ISACSR bus cycles are identical
to all other PCnet-ISA
Boot PROM Cycles
The Boot PROM is an 8-bit PROM connected to the
PCnet-ISA
can occupy up to 64 Kbytes of address space. In Shared
Memory Mode, an external address comparator is re-
sponsible for asserting BPAM to the PCnet-ISA+
controller. BPAM is intended to be a perfect decode of
the boot PROM address space, i.e. LA17-23, SA16. The
LA bus must be latched with BALE in order to provide
stable signal for BPAM. REF inactive must be used by
the external logic to gate boot PROM address decoding.
This same logic must assert MEMCS16 to the ISA bus if
16-bit Boot PROM bus cycles are desired.
The PCnet-ISA
bus cycles for the boot PROM. A 16-bit boot PROM bus
cycle begins with the Permanent Master driving the ad-
dresses valid and MEMR active. (AEN is not involved in
memory cycles). External hardware would assert BPAM
and MEMCS16. The PCnet-ISA
combination of signals, drives IOCHRDY LOW, and
reads two bytes out of the boot PROM. The data bytes
read from the PROM are driven by the PCnet-ISA+ con-
troller onto SD0-15 and IOCHRDY is released. This
condition is maintained until MEMR goes inactive, at
which time the access cycle ends.
The PCnet-ISA
cle operation for all resource (registers, PROMs,
SRAM) if SBHE has been left unconnected, such as in
the case of an 8-bit system like the PC/XT.
The BPCS signal generated by the PCnet-ISA
ler is three 20 MHz clock cycles wide (350 ns). Including
delays, the Boot PROM has 275 ns to respond to the
BPCS signal from the PCnet-ISA
is intended to be connected to the CS pin on the boot
PROM, with the PROM OE pin tied to ground.
Static RAM Cycles
The shared memory SRAM is an 8-bit device connected
to the PCnet-ISA
cupy up to 64 Kbytes of address space. In Shared
Memory Mode, an external address comparator is re-
sponsible for asserting SMAM to the PCnet-ISA
controller. SMAM is intended to be a perfect decode of
the SRAM address space, i.e. LA17-23, SA16 for 64
Kbytes of SRAM. The LA signals must be latched by
BALE in order to provide a stable decode for SMAM.
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controller Private Data Bus (PRDB), and
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controller will perform 8-bit ISA bus cy-
controller assumes 16-bit ISA memory
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controller Private Bus, and can oc-
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controller register bus cycles.
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controller detects this
controller. This signal
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control-
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