am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 25

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

PIN DESCRIPTION:
SHARED MEMORY MODE
ISA Interface
AEN
Address Enable
This signal must be driven LOW when the bus performs
an I/O access to the device.
IOCHRDY
I/O Channel Ready
When the PCnet-ISA
HIGH on IOCHRDY indicates that valid data exists on
the data bus for reads and that data has been latched for
writes.
IOCS16
I/O Chip Select 16
When an I/O read or write operation is performed, the
PCnet-ISA
that the chip supports a 16-bit operation at this address.
(If the motherboard does not receive this signal, then the
motherboard will convert a 16-bit access to two 8-bit
accesses.)
The PCnet-ISA
fication that recommends this function be implemented
as a pure decode of SA0-9 and AEN, with no depend-
ency on IOR, or IOW; however, some PC/AT clone
systems are not compatible with this approach. For this
reason, the PCnet-ISA
be configured to run 8-bit I/O on all machines. Since
data is moved by memory cycles there is virtually no per-
formance loss incurred by running 8-bit I/O and
compatibility problems are virtually eliminated. The
PCnet-ISA
only I/O by clearing Bit 0 in Plug and Play Register F0.
IOR
I/O Read
To perform an Input/Output Read operation on the de-
vice IOR must be asserted. IOR is only valid if the AEN
signal is LOW and the external address matches the
PCnet-ISA+ controller ’s predefined I/O address loca-
tion. If valid, IOR indicates that a slave read operation is
to be performed.
IOW
I/O Write
To perform an Input/Output write operation on the de-
vice IOW must be asserted. IOW is only valid if AEN
signal is LOW and the external address matches the
PCnet-ISA+ controller’s predefined I/O address loca-
tion. If valid, IOW indicates that a slave write operation
is to be performed.
IRQ3, 4, 5, 9, 10, 11, 15
Interrupt Request
An attention signal which indicates that one or more of
the following status flags is set: BABL, MISS, MERR,
RINT, IDON or TXSTRT. All status flags have a mask bit
+
+
controller will drive this pin LOW to indicate
controller can be configured to run 8-bit-
+
controller follows the IEEE P996 speci-
+
controller is being accessed, a
+
controller is recommended to
Input
Output
Input/Output
Input
Input
Output
P R E L I M I N A R Y
Am79C961
which allows for suppression of IRQ assertion. These
flags have the following meaning:
MEMR
Memory Read
MEMR goes LOW to perform a memory read operation.
MEMW
Memory Write
MEMW goes LOW to perform a memory write
operation.
RESET
Reset
When RESET is asserted HIGH, the PCnet-ISA+ con-
troller performs an internal system reset. RESET must
be held for a minimum of 10 XTAL1 periods before being
deasserted. While in a reset state, the PCnet-ISA
troller will tristate or deassert all outputs to predefined
reset levels. The PCnet-ISA
upon power-up.
SA0-15
System Address Bus
This bus carries the address inputs from the system ad-
dress bus. Address data is stable during command
active cycle.
SBHE
System Bus High Enable
This signal indicates the HIGH byte of the system data
bus is to be used. There is a weak pull-up resistor on this
pin. If the PCnet-ISA+ controller is installed in an 8-bit
only system like the PC/XT, SBHE will always be HIGH
and the PCnet-ISA+ controller will perform only 8-bit op-
erations. There must be at least one LOW going edge on
this signal before the PCnet-ISA+ controller will perform
16-bit operations.
SD0-15
System Data Bus
This bus is used to transfer data to and from the
PCnet-ISA
data bus. SD0-15 is driven by the PCnet-ISA
when performing slave read operations.
Likewise, the data on SD0-15 is latched by the
PCnet-ISA
operations.
BABL
RCVCCO
JAB
MISS
MERR
MPCO
RINT
IDON
TXSTRT
+
+
controller to system resources via the ISA
controller when performing slave write
Babble
Receive Collision Count Overflow
Jabber
Missed Frame
Memory Error
Missed Packet Count Overflow
Receive Interrupt
Initialization Done
Transmit Start
+
controller resets itself
Input
Input
Input
Input
Input
Input/Output
+
AMD
controller
1-499
+
con-