am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 52

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

PCnet-ISA
therefore, the condition is treated as a fatal error. To
avoid this situation, the system should always set the
transmit chain descriptor own bits in reverse order.
If the PCnet-ISA
in a chain, it will gradually empty the contents of the first
buffer (as the bytes are needed by the transmit opera-
tion), perform a single-cycle DMA transfer to update the
status (reset the OWN bit in TMD1) of the first descrip-
tor, and then it may perform one data DMA access on
the second buffer in the chain before executing another
lookahead operation. (i.e. a lookahead to the third
descriptor.)
The PCnet-ISA
in the transmit FIFO. Call them packet “X” and packet
“Y”, where “Y” is after “X”. Assume that packet “X” is
currently being transmitted. Because the PCnet-ISA
controller can perform lookahead data transfer over an
ENP, it is possible for the PCnet-ISA+ controller to up-
date a TDTE in a buffer belonging to packet “Y” while
packet “X” is being transmitted if packet “Y” uses data
chaining. This operation will result in non-sequential
TDTE accesses as packet “X” completes transmission
and the PCnet-ISA
packet “X”’s TDTE is before the TDTE accessed as part
of the lookahead data transfer from packet “Y”.
This should not cause any problem for properly written
software which processes buffers in sequence, waiting
for ownership before proceeding.
If an error occurs in the transmission before all of the
bytes of the current buffer have been transferred, then
TMD2 and TMD1 of the current buffer will be written; in
that case, data transfers from the next buffer will not
commence. Instead, following the TMD2/TMD1 update,
the PCnet-ISA
packet, if any, skipping over the rest of the packet which
experienced an error, including chained buffers.
This is done by returning to the polling microcode where
it will immediately access the next descriptor and find
the condition OWN = 1 and STP = 0 as described earlier.
In that case, the PCnet-ISA
bit for this descriptor and continue in like manner until a
descriptor with OWN=0 (no more transmit packets in the
ring) or OWN = 1 and STP = 1 (the first buffer of a new
packet) is reached.
At the end of any transmit operation, whether successful
or with errors, and the completion of the descriptor up-
dates, the PCnet-ISA
another poll operation. As described earlier, this poll op-
eration will begin with a check of the current RDTE,
unless the PCnet-ISA
scriptor. Then the PCnet-ISA
polling the next TDTE. If the transmit descriptor OWN bit
has a zero value, then the PCnet-ISA
sume poll time count incrementation. If the transmit
descriptor OWN bit has a value of ONE, then the
PCnet-ISA
transmit data and initiate a transmission. This end-of-
1-526
AMD
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controller in the transmit descriptor ring and
controller will begin filling the FIFO with
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controller can queue up to two packets
controller will go to the next transmit
controller does own the second TDTE
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controller writes out its status, since
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controller already owns that de-
controller will always perform
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controller will reset the own
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controller will proceed to
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controller will re-
P R E L I M I N A R Y
Am79C961
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operation poll avoids inserting poll time counts between
successive transmit packets.
Whenever the PCnet-ISA
mit packet (either with or without error) and writes the
status information to the current descriptor, then the
TINT bit of CSR0 is set to indicate the completion of a
transmission. This causes an interrupt signal if the IENA
bit of CSR0 has been set and the TINTM bit of CSR3
is reset.
Receive Descriptor Table Entry (RDTE)
If the PCnet-ISA
rent and the next Receive Descriptor Table Entry, then
the PCnet-ISA
to the polling sequence described above. If the receive
descriptor ring length is 1, there is no next descriptor,
and no look ahead poll will take place.
If a poll operation has revealed that the current and the
next RDTE belongs to the PCnet-ISA
additional poll accesses are not necessary. Future poll
operations will not include RDTE accesses as long as
the PCnet-ISA
rent and the next RDTE.
When receive activity is present on the channel, the
PCnet-ISA
the message to arrive. It then decides whether to accept
or reject the packet based on all active addressing
schemes. If the packet is accepted the PCnet-ISA
troller checks the current receive buffer status register
CRST (CSR40) to determine the ownership of the cur-
rent buffer.
If ownership is lacking, then the PCnet-ISA
will immediately perform a (last ditch) poll of the current
RDTE. If ownership is still denied, then the PCnet-ISA
controller has no buffer in which to store the incoming
message. The MISS bit will be set in CSR0 and an inter-
rupt will be generated if IENA = 1 (CSR0) and MISSM =
0 (CSR3). Another poll of the current RDTE will not oc-
cur until the packet has finished.
If the PCnet-ISA
a normal poll or the last-ditch effort described in the
above paragraph) of the current RDTE shows valid own-
ership, then it proceeds to a poll of the next RDTE.
Following this poll, and regardless of the outcome of this
poll, transfers of receive data from the FIFO may begin.
Regardless of ownership of the second receive descrip-
tor, the PCnet-ISA
receive data DMA transfers to the first buffer, using
burst-cycle DMA transfers. If the packet length exceeds
the length of the first buffer, and the PCnet-ISA
ler does not own the second buffer, ownership of the
current descriptor will be passed back to the system by
writing a zero to the OWN bit of RMD1 and status will be
written indicating buffer (BUFF = 1) and possibly over-
flow (OFLO = 1) errors.
If the packet length exceeds the length of the first (cur-
rent) buffer, and the PCnet-ISA
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controller waits for the complete address of
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controller will continue to poll according
controller retains ownership to the cur-
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controller sees that the last poll (either
controller does not own both the cur-
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controller will continue to perform
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controller completes a trans-
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controller does own the
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controller, then
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controller
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control-
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con-
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