am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 88

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

1-562
9-8 XMTFW[1:0]
7-0
AMD
DMABR
XMTFW[1:0]
XMTSP[1:0]
00
01
10
11
00
01
10
11
write its data until at least 64
bytes (or the entire frame if <64
bytes) have been transmitted
onto the network. This ensures
that for collisions within the slot
time window, transmit data need
not be re-written to the transmit
FIFO, and re-tries will be handled
autonomously by the MAC. This
bit is read/write accessible only
when the STOP bit is set.
Transmit
XMTFW specifies the point at
which
based upon the number of write
cycles that could be performed to
the transmit FIFO without FIFO
overflow. Transmit DMA is al-
lowed at any time when the
number of write cycles specified
by XMTFW could be executed
without causing transmit FIFO
overflow. XMTFW is set to a
value of 00b (8 cycles) after hard-
ware
accessible only when STOP bit is
set.
DMA Burst Register. This regis-
ter
allowable number of transfers to
system memory that the Bus In-
terface will perform during a
single DMA cycle. The Burst
Register is not used to limit the
number
Descriptor transfers. A value of
zero will be interpreted as one
transfer. During RESET a value
of 16 is loaded in the BURST reg-
ister. If DMAPLUS (CSR4.14) is
set, the DMA Burst Register is
disabled.
When the Bus Activity Timer reg-
ister
enabled, the PCnet-ISA
ler will relinquish the bus when
either the time specified in
DMABAT has elapsed or the
contains
(CSR82:
transmit
RESET.
of
FIFO
Bytes Written
Write Cycles
transfers
Reserved
the
112
DMABAT)
16
64
16
32
DMA
4
8
Watermark.
Read/write
maximum
P R E L I M I N A R Y
+
control-
during
stops,
Am79C961
is
CSR82: Bus Activity Timer
Bit
15-0 DMABAT
CSR84-85: DMA Address
Bit
31-0
DMABA
Name
Name
number of transfers specified in
DMABR have occured.
Read/write accessible only when
STOP bit is set.
Bus Activity Timer. If the TIMER
bit in CSR4 is set, this register
contains the maximum allowable
time that the PCnet-ISA
ler will take up on the system bus
during FIFO data transfers in
each bus mastership period. The
DMABAT starts counting upon
receipt of DACK from the host
system. The DMABAT Register
does not limit the number of
transfers
transfers.
A value of zero will limit the
PCnet-ISA
cycle per mastership period. A
non-zero value is interpreted as
an unsigned number with a reso-
lution of 100 ns. For instance, a
value of 51 s would be pro-
grammed with a value of 510.
When the TIMER bit in CSR4 is
set, DMABAT is enabled and
must be initialized by the user.
The DMABAT register is unde-
fined until written.
When the Bus Activity Timer reg-
ister
enabled, the PCnet-ISA+ con-
trol- ler will relinquish the bus
when either the time specified in
DMABAT has elapsed or the
number of transfers specified in
DMABR have occured. When
ENTST (CSR4.15) is asserted,
all writes to this register will auto-
matically perform a decrement
cycle.
Read/write accessible only when
STOP bit is set.
DMA Address Register.
This register contains the ad-
dress of system memory for the
current DMA cycle. The Bus In-
terface Unit controls the Address
(CSR82:
Description
Description
+
controller to one bus
during
DMABAT)
Descriptor
+
control-
is