am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 98

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

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9
8
7-0
RMD2
Bit
15-12 ONES
11-0
RMD3
Bit
15-12
11-0
AMD
HADR
MCNT
BCNT
Name
Name
STP
ENP
RES
If a Buffer Error occurs, an Over-
flow Error may also occur
internally in the FIFO, but will not
be reported in the descriptor
status entry unless both BUFF
and OFLO errors occur at the
same time. BUFF is written by
the PCnet-ISA
START OF PACKET indicates
that this is the first buffer used by
the PCnet-ISA
frame. It is used for data chaining
buffers. STP is written by the
PCnet-ISA
operation. In SRPINT Mode
(CSR3.5 set to 1) this bit is writ-
ten by the driver.
END OF PACKET indicates that
this is the last buffer used by the
PCnet-ISA
frame. It is used for data chaining
buffers. If both STP and ENP are
set, the frame fits into one buffer
and there is no data chaining.
ENP is written by the PCnet-ISA
controller.
The HIGH ORDER 8 address
bits of the buffer pointed to by this
descriptor. This field is written by
the host and is not changed by
the PCnet-ISA
MUST BE ONES. This field is
written by the host and un-
changed by the PCnet-ISA
controller.
BUFFER BYTE COUNT is the
length of the buffer pointed to by
this descriptor, expressed as the
two’s complement of the length
of the buffer. This field is written
by the host and is not changed by
the PCnet-ISA
RESERVED and read as zeros.
MESSAGE BYTE COUNT is the
length in bytes of the received
message, expressed as an un-
signed binary integer. MCNT is
valid only when ERR is clear and
ENP is set. MCNT is written by
the PCnet-ISA
cleared by the host.
Description
Description
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controller in normal
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controller for this
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controller.
controller and
P R E L I M I N A R Y
Am79C961
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Transmit Descriptors
The Transmit Descriptor Ring Entries (TDREs) are com-
posed of four transmit message fields (TMD0-3).
Together they contain the following information:
Note that bit 13 of TMD1, which was formerly a reserved
bit in the LANCE (Am7990), is assigned a new meaning,
ADD_FCS.
TMD0
Holds LADR [15:0]. This is combined with HADR [7:0] in
TMD1 to form a 24-bit address of the buffer pointed to by
this descriptor table entry. There are no restrictions on
buffer byte alignment or length.
TMD1
Bit
15
14
13
The address of the actual message data buffer in
user or host memory
The length of the message buffer
Status information indicating the condition of the
buffer. The eight most significant bits of TMD1
(TMD1[15:8]) are collectively termed the STATUS
of the transmit descriptor.
ADD_FCS
Name
OWN
ERR
This bit indicates that the de-
scriptor entry is owned by the
host
PCnet-ISA
The host sets the OWN bit after
filling the buffer pointed to by the
descriptor entry. The PCnet-ISA
controller clears the OWN bit af-
ter transmitting the contents of
the buffer. Both the PCnet-ISA
controller and the host must not
alter a descriptor entry after it has
relinquished ownership.
ERR is the OR of UFLO, LCOL,
LCAR, or RTRY. ERR is written
by the PCnet-ISA
This bit is set in the current de-
scriptor when the error occurs,
and therefore may be set in any
descriptor of a chained buffer
transmission.
ADD_FCS dynamically controls
the generation of FCS on a frame
by frame basis. It is valid only if
the STP bit is set. When
ADD_FCS is set, the state of
DXMTFCS is ignored and trans-
mitter
activated. When ADD_FCS = 0,
FCS generation is controlled by
DXMTFCS. ADD_FCS is written
(OWN=0)
FCS
Description
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controller (OWN=1).
generation
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controller.
by
the
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