am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 95

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

ISACSR7: LED3 Status
Bit
15
14-8
7
6
5
4
3
2
1
0
RCVADDM
RVPOL E
LEDOUT
XMT E
RCV E
COL E
JAB E
Name
RES
PSE
RES
ISACSR7 controls the func-
tion(s)
displays. Multiple functions can
be simultaneously enabled on
this LED pin. The LED display will
indicate the logical OR of the
enabled functions. ISACSR7 de-
faults to Transmit Status (XMT)
with pulse stretcher enabled
(PSE = 1) and is fully program-
mable.
Indicates
stretched) state of the function(s)
generated. Read only.
Reserved locations. Read and
written as zero.
Pulse Stretcher Enable. Extends
the LED illumination for each en-
abled function occurrence.
0 is disabled, 1 is enabled.
Reserved locations. Read and
written as zero.
Receive Address Match. This bit
when set allows for LED control
of only receive packets that
match internal address match.
Enable Transmit Status Signal.
Indicates PCnet-ISA
transmit activity .
0 disables the signal, 1 enables
the signal.
Enable Receive Polarity Signal.
Enables LED pin assertion when
receive polarity is correct on the
10BASE-T port. Clearing the bit
indicates this function is to be
ignored.
Enable Receive Status Signal.
Indicates receive activity on the
network.
0 disables the signal, 1 enables
the signal.
Enable Jabber Signal. Indicates
the PCnet-ISA
bering on the network.
0 disables the signal, 1 enables
the signal.
Enable Collision Signal. Indi-
cates collision activity on the
network.
0 disables the signal, 1 enables
the signal.
that
Description
the
+
the
controller is jab-
current
+
LED3
controller
P R E L I M I N A R Y
(non-
Am79C961
pin
ISACSR8: Software Configuration Register
(Read-Only Register)
Initialization Block
The figure below shows the Initialization Block memory
configuration. Note that the Initialization Block must be
based on a word (16-bit) boundary.
RLEN and TLEN
The TLEN and RLEN fields in the initialization block are
3 bits wide, occupying bits 15,14, and 13, and the value
in these fields determines the number of Transmit and
Receive Descriptor Ring Entries (DRE) which are used
in the descriptor rings. Their meaning is as follows:
IADR+00
IADR+02
IADR+04
IADR+06
IADR+08
IADR+10
IADR+12
IADR+14
IADR+16
IADR+18
IADR+20
IADR+22
Address
15–12
11–8
7–4
3
2–0
Bit
RLEN
TLEN
Read-only image of SR_AM(3:0) of P&P
register 0x48 - 0x49.
Read-only image of BP_AM(3:0) of P&P
register 0x40 - 0x41.
Read-only image of IRQSEL(3:0) of P&P
register 0x70.
Reserved, written with zero,
read as undefined.
Read-only image of DMASEL(2:0) of
P&P register 0x74.
15–12
Bits
MODE 15-00
PADR 15-00
PADR 31-16
PADR 47-32
LADRF 15-00
LADRF 31-16
LADRF 47-32
LADRF 63-48
RDRA 15-00
RES
RES
11–8
Bits
TDRA 15-00
Description
RDRA 23-16
TDRA 23-16
Bits
7–4
AMD
Bits
3–0
1-569