am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 69

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

The PCnet-ISA
bus cycles for the SRAM, so this same logic must assert
MEMCS16 to the ISA bus if 16-bit bus cycles are to be
supported.
A 16-bit SRAM bus cycle begins with the Permanent
Master driving the addresses valid, REF inactive, and
either MEMR or MEMW active. (AEN is not involved in
memory cycles). External hardware would assert
SMAM and MEMCS16. The PCnet-ISA
tects this combination of signals and initiates the SRAM
access.
In a write cycle, the PCnet-ISA
data into an internal holding register, allowing the ISA
bus cycle to finish normally. The data in the holding reg-
ister will then be written to the SRAM without the need
for ISA bus control. In the event the holding register is
already filled with unwritten SRAM data, the PCnet-ISA
controller will extend the ISA write cycle by driving
IOCHRDY LOW until the unwritten data is stored in the
SRAM. The current ISA bus cycle will then complete
normally.
In a read cycle, the PCnet-ISA
the Private Bus. If it is unavailable, the PCnet-ISA
troller drives IOCHRDY LOW. The PCnet-ISA
controller compares the 16 bits of address on the Sys-
tem Address Bus with that of a data word held in an
internal pre-fetch register.
If the address does not match that of the prefetched
SRAM data, then the PCnet-ISA
IOCHRDY LOW and reads two bytes from the SRAM.
The PCnet-ISA
addressed data location had been prefetched.
If the internal prefetch buffer contains the correct data,
then the pre-fetch buffer data is driven on the System
Data bus. If IOCHRDY was previously driven LOW due
to either Private Data Bus arbitration or SRAM access,
then it is released HIGH. The PCnet-ISA
mains in this state until MEMR is de-asserted, at which
time the PCnet-ISA
of the SRAM. In this way memory read wait states can
be minimized.
The PCnet-ISA
SRAM between ISA bus cycles. The SRAM is
prefetched in an incrementing word address fashion.
Prefetched data are invalidated by any other activity on
the Private Bus, including Shared Memory Writes by
either the ISA bus or the network interface, and also ad-
dress and boot PROM reads.
The only way to configure the PCnet-ISA+ controller for
8-bit ISA bus cycles for SRAM accesses is to configure
the entire PCnet-ISA
bus cycles. This is accomplished by leaving the SBHE
pin disconnected. The PCnet-ISA
form 8-bit ISA bus cycle operation for all resources
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controller then proceeds as though the
controller assumes 16-bit ISA memory
controller performs prefetches of the
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controller performs a new prefetch
controller to support only 8-bit ISA
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controller arbitrates for
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controller stores the
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controller will per-
controller drives
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controller de-
controller re-
P R E L I M I N A R Y
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con-
Am79C961
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(registers, PROMs, SRAM) if SBHE has never been
driven active since the last RESET, such as in the case
of an 8-bit system like the PC/XT. In this case, the exter-
nal address decode logic must not assert MEMCS16 to
the ISA bus, which will be the case if MEMCS16 is left
unconnected. It is possible to manufacture a dual 8/16
bit PCnet-ISA
MEMCS16 and SBHE signals do not exist in the PC/XT
environment.
At the memory device level, each SRAM Private Bus
read cycle takes two 50 ns clock periods for a maximum
read access time of 75 ns. The timing looks like this:
The address and SROE go active within 20 ns of the
clock going HIGH. Data is required to be valid 5 ns be-
fore the end of the second clock cycle. Address and
SROE have a 0 ns hold time after the end of the second
clock cycle. Note that the PCnet-ISA
not normally provide a separate SRAM CS signal;
SRAM CS must always be asserted.
SRAM Private Bus write cycles require three 50 ns clock
periods to guarantee non-negative address setup and
hold times with regard to SRWE. The timing is illustrated
as follows:
Address and data are valid 20 ns after the rising edge of
the first clock period. SRWE goes active 20 ns after the
falling edge of the first clock period. SRWE goes inactive
20 ns after the falling edge of the third clock period.
Address and data remain valid until the end of the third
clock period. Rise and fall times are nominally 5 ns.
(20 MHz)
XTAL1
(20 MHz)
Address/
(20 MHz)
Address/
Address
SRWE
XTAL1
SRWE
SROE
Data
XTAL
Data
Static RAM Write Cycle
Static RAM Read Cycle
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controller adapter card, as the
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controller does
AMD
18183B-18
18183B-17
16907B-11
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