am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 48

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

Once the BIU has been granted bus mastership, it will
perform four data transfer cycles (eight bytes) before re-
linquishing the bus. The four transfers within the
mastership period will always be read cycles to
contiguous addresses. There are 12 words to transfer
so there will be three bus mastership periods.
2. Descriptor DMA Transfers
Once the BIU has been granted bus mastership, it will
perform the appropriate number of data transfer cycles
before relinquishing the bus. The transfers within the
mastership period will always be of the same type
(either all read or all write), but may be to non-
contiguous addresses. Only the bytes which need to be
read or written are accessed.
3. Burst-Cycle DMA Transfers
Once the BIU has been granted bus mastership, it will
perform a series of consecutive data transfer cycles be-
fore relinquishing the bus. Each data transfer will be
performed sequentially, with the issue of the address,
and the transfer of the data with appropriate output sig-
nals to indicate selection of the active data bytes during
the transfer. All transfers within the mastership cycle will
be either read or write cycles, and will be to contiguous
addresses. The number of data transfer cycles within
the burst is dependent on the programming of the
DMAPLUS option (CSR4, bit 14).
If DMAPLUS = 0, a maximum of 16 transfers will be per-
formed. This may be changed by writing to the burst
register (CSR80), but the default takes the same
amount of time as the Am2100 family of LANCE-based
boards, a little over 5 s.
If DMAPLUS = 1, the burst will continue until the FIFO is
filled to its high threshold (32 bytes in transmit opera-
tion) or emptied to its low threshold (16 bytes in receive
operation). The exact number of transfer cycles in this
case will be dependent on the latency of the system bus
to the BIU’s mastership request and the speed of
bus operation.
Buffer Management Unit (BMU)
The buffer management unit is a micro-coded 20 MHz
state machine which implements the initialization block
and the descriptor architecture.
Initialization
PCnet-ISA
of the initialization block in memory to obtain the operat-
ing parameters. The initialization block is read when the
INIT bit in CSR0 is set. The INIT bit should be set before
or concurrent with the STRT bit to insure correct opera-
tion. Four words at a time are read and the bus is
released at the end of each block of reads, for a total of
three arbitration cycles. Once the initialization block has
been read in and processed, the BMU knows where the
receive and transmit descriptor rings are. On completion
of the read operation and after internal registers have
been updated, IDON will be set in CSR0, and an inter-
rupt generated if IENA is set.
1-522
AMD
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controller initialization includes the reading
P R E L I M I N A R Y
Am79C961
The Initialization Block is vectored by the contents of
CSR1 (least significant 16 bits of address) and CSR2
(most significant 8 bits of address). The block contains
the user defined conditions for PCnet-ISA
operation, together with the address and length
information to allow linkage of the transmit and receive
descriptor rings.
There is an alternative method to initialize the
PCnet-ISA
initialization block in memory, data can be written di-
rectly into the appropriate registers. Either method may
be used at the discretion of the programmer. If the regis-
ters are written to directly, the INIT bit must not be set, or
the initialization block will be read in, thus overwriting
the previously written information. Please refer to
Appendix D for details on this alternative method.
Reinitialization
The transmitter and receiver section of the PCnet-ISA
controller can be turned on via the initialization block
(MODE Register DTX, DRX bits; CSR15[1:0]). The
state of the transmitter and receiver are monitored
through CSR0 (RXON, TXON bits). The PCnet-ISA
controller should be reinitialized if the transmitter and/or
the receiver were not turned on during the original in-
itialization and it was subsequently required to activate
them, or if either section shut off due to the detection of
an error condition (MERR, UFLO, TX BUFF error).
Reinitialization may be done via the initialization block or
by setting the STOP bit in CSR0, followed by writing to
CSR15, and then setting the START bit in CSR0. Note
that this form of restart will not perform the same in the
PCnet-ISA
PCnet-ISA
descriptor pointers with their respective base ad-
dresses.This means that the software must clear the
descriptor’s own bits and reset its descriptor ring point-
ers before the restart of the PCnet-ISA controller. The
reload of descriptor base addresses is performed in the
LANCE only after initialization, so a restart of the
LANCE without initialization leaves the LANCE pointing
at the same descriptor locations as before the restart.
Buffer Management
Buffer management is accomplished through message
descriptor entries organized as ring structures in mem-
ory. There are two rings, a receive ring and a transmit
ring. The size of a message descriptor entry is 4 words
(8 bytes).
Descriptor Rings
Each descriptor ring must be organized in a contiguous
area of memory. At initialization time (setting the INIT bit
in CSR0), the PCnet-ISA
fined base address for the transmit and receive
descriptor rings, which must be on an 8-byte boundary,
as well as the number of entries contained in the de-
scriptor rings. By default, a maximum of 128 ring entries
is permitted when utilizing the initialization block, which
uses values of TLEN and RLEN to specify the transmit
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controller as in the LANCE. In particular, the
controller reloads the transmit and receive
controller. Instead of initialization via the
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controller reads the user-de-
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controller
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