am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 93

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

13–5
4
3
2
1
0
SHFBUSY
EE_EN
EECS
DI/DO
N/A
SK
PCnet-ISA
figuration. This command must
be last write to ISACSR3 Regis-
ter. PCnet-ISA
to any slave commands while
loading the EE_PROM register.
EE_LOAD will be reset with a
zero after EE_PROM is read. It
takes approximately, 1.4 ms for
serial EEPROM load process to
complete.
Reserved. Read and written as
zeros.
EEPROM Enable. When EE_EN
is written with a one, the lower
three bits of PRDB becomes SK,
DI and DO, respectively. EECS
and SHFBUSY are controlled by
the software select bits. This bit
must be written with a one to
write to or read from the
EEPROM.
be in the STOP state when
EE_EN is written. When EN_EN
is cleared, DI/DO, SK, EECS and
SHFBUSY have no control.
Shift Busy. SHFBUSY allows for
the control of the SHFBUSY pin.
When
SHFBUSY goes high provided
EE_EN is a 1. When a zero is
written, SHFBUSY is held to a
zero. When EE_EN is cleared,
SHFBUSY will maintain the last
value programmed. (Refer to Bit
4 above, EE_EN, for detailed use
of this bit.)
EEPROM Chip Select. EECS as-
serts the chip select to the Serial
EEPROM. (Refer to Bit 4 above,
EE_EN, for detailed use of this
bit.)
Serial Shift Clock. SK controls
the SK input to the Serial
EEPROM and the optional Exter-
nal Shift Logic. (Refer to Bit 4
above, EE_EN, for detailed use
of this bit.)
Serial Shift Data In and Serial
Shift Data Out. When written, this
bit controls the DI input of the se-
rial EEPROM. When read, this bit
represents the DO value of the
serial EEPROM. (Refer to Bit 4
above, EE_EN, for detailed use
of this bit.)
a
+
, performing self con-
PCnet-ISA
one
+
will not respond
is
P R E L I M I N A R Y
+
written,
should
Am79C961
ISACSR4: LED0 Status (Link Integrity)
Bit
15
14-0
ISACSR5: LED1 Status
Bit
15
14-8
7
6
5
4
RCVADDM
LEDOUT
LNKST
XMT E
Name
Name
RES
RES
RES
PSE
ISACSR4 is a non-programma-
ble register that uses one bit to
reflect the status of the LED0 pin.
This pin defaults to twisted pair
MAU Link Status (LNKST) and is
not programmable.
LNKST is a read-only register bit
that indicates whether the Link
Status LED is asserted. When
LNKST is read as zero, the Link
Status LED is not asserted.
When LNKST is read as one, the
Link Status LED is asserted, indi-
cating good 10BASE-T integrity.
Reserved locations. Written as
zero, read as undefined.
ISACSR5 controls the func-
tion(s)
displays. Multiple functions can
be simultaneously enabled on
this LED pin. The LED display will
indicate the logical OR of the en-
abled
defaults to Receive Status (RCV)
with pulse stretcher enabled
(PSE = 1) and is fully program-
mable.
Indicates
stretched) state of the function(s)
generated. Read only.
Reserved locations. Read and
written as zero.
Pulse Stretcher Enable. Extends
the LED illumination for each en-
abled function occurrence.
0 is disabled, 1 is enabled.
Reserved locations. Read and
written as zero.
Receive Address Match. This bit
when set allows for LED control
of only receive packets which
match internal address match.
Enable Transmit Status Signal.
Indicates PCnet-ISA
transmit activity .
that
functions.
Description
Description
the
the
current
+
LED1
AMD
ISACSR5
controller
1-567
(non-
pin