am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 16

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

1-490
PIN DESCRIPTION: BUS MASTER MODE
These pins are part of the bus master mode. In order to
understand the pin descriptions, definition of some
terms from a draft of IEEE P996 are included.
IEEE P996 Terminology
Alternate Master: Any device that can take control of
the bus through assertion of the MASTER signal. It has
the ability to generate addresses and bus control signals
in order to perform bus operations. All Alternate Mas-
ters must be 16 bit devices and drive SBHE.
Bus Ownership: The Current Master possesses bus
ownership and can assert any bus control, address and
data lines.
Current Master: The Permanent Master, Temporary
Master or Alternate Master which currently has owner-
ship of the bus.
Permanent Master: Each P996 bus will have a device
known as the Permanent Master that provides certain
signals and bus control functions as described in Sec-
tion 3.5 (of the IEEE P996 spec), “Permanent Master”.
The Permanent Master function can reside on a Bus
Adapter or on the backplane itself.
Temporary Master: A device that is capable of gener-
ating a DMA request to obtain control of the bus and
directly asserting only the memory and I/O strobes dur-
ing bus transfer. Addresses are generated by the DMA
device on the Permanent Master.
ISA Interface
AEN
Address Enable
This signal must be driven LOW when the bus performs
an I/O access to the device.
BALE
Used to latch the LA20–23 address lines.
DACK 3, 5-7
DMA Acknowledge
Asserted LOW when the Permanent Master acknowl-
edges a DMA request. When DACK is asserted the
PCnet-ISA
asserting the MASTER signal.
DRQ 3, 5-7
DMA Request
When the PCnet-ISA
DMA transfer, it asserts DRQ. The Permanent Master
acknowledges DRQ with assertion of DACK. When the
PCnet-ISA
serts DRQ.
AMD
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controller becomes the Current Master by
controller does not need the bus it deas-
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controller needs to perform a
Input
Input
Output
P R E L I M I N A R Y
Am79C961
Because of the operation of the Plug and Play registers,
the DMA Channels on the PCnet-ISA
to specific DRQ and DACK signals on the PC/AT bus.
IOCHRDY
I/O Channel Ready
When the PCnet-ISA
IOCHRDY HIGH indicates that valid data exists on the
data bus for reads and that data has been latched for
writes. When the PCnet-ISA
Master on the ISA bus, it extends the bus cycle as long
as IOCHRDY is LOW.
IOCS16
I/O Chip Select 16
When an I/O read or write operation is performed, the
PCnet-ISA
indicate that the chip supports a 16-bit operation at this
address. (If the motherboard does not receive this sig-
nal, then the motherboard will convert a 16-bit access to
two 8-bit accesses.)
The PCnet-ISA
fication that recommends this function be implemented
as a pure decode of SA0-9 and AEN, with no depend-
ency on IOR, or IOW; however, some PC/AT clone
systems are not compatible with this approach. For this
reason, the PCnet-ISA
be configured to run 8-bit I/O on all machines. Since
data is moved by memory cycles there is virtually no per-
formance loss incurred by running 8-bit I/O and
compatibility problems are virtually eliminated. The
PCnet-ISA
only I/O by clearing Bit 0 in Plug and Play register F0.
IOR
I/O Read
IOR is driven LOW by the host to indicate that an Input/
Output Read operation is taking place. IOR is only valid
if the AEN signal is LOW and the external address
matches the PCnet-ISA
dress location. If valid, IOR indicates that a slave read
operation is to be performed.
IOW
I/O Write
IOW is driven LOW by the host to indicate that an Input/
Output Write operation is taking place. IOW is only valid
if AEN signal is LOW and the external address matches
the PCnet-ISA
location. If valid, IOW indicates that a slave write opera-
tion is to be performed.
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controller will drive the IOCS16 pin LOW to
controller can be configured to run 8-bit-
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controller follows the IEEE P996 speci-
controller’s predefined I/O address
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controller is being accessed,
controller is recommended to
controller’s predefined I/O ad-
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controller is the Current
Input/Output
Output
Input
Input
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must be attached