am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 49

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

and receive descriptor ring lengths. However, the ring
lengths can be manually defined (up to 65535) by writing
the transmit and receive ring length registers
(CSR76,78) directly.
Each ring entry contains the following information:
Receive descriptor entries are similar (but not identical)
to transmit descriptor entries. Both are composed of four
registers, each 16 bits wide for a total of 8 bytes.
To permit the queuing and de-queuing of message buff-
ers, ownership of each buffer is allocated to either the
PCnet-ISA
the descriptor status information, either TMD or RMD
(see section on TMD or RMD), is used for this purpose.
“Deadly Embrace” conditions are avoided by the owner-
ship mechanism. Only the owner is permitted to
The address of the actual message data buffer
in user or host memory
The length of the message buffer
Status information indicating the condition of
the buffer
+
controller or the host. The OWN bit within
P R E L I M I N A R Y
Am79C961
relinquish ownership or to write to any field in the
descriptor entry. A device that is not the current owner of
a descriptor entry cannot assume ownership or change
any field in the entry.
Descriptor Ring Access Mechanism
At initialization, the PCnet-ISA
base address of both the transmit and receive descriptor
rings into CSRs for use by the PCnet-ISA+ controller
during subsequent operation.
When transmit and receive functions begin, the base
address of each ring is loaded into the current descriptor
address registers and the address of the next descriptor
entry in the transmit and receive rings is computed and
loaded into the next descriptor address registers.
+
controller reads the
AMD
1-523