am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 83

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

1
0
CSR16: Initialization Block Address Lower
Bit
15-0
CSR17: Initialization Block Address Upper
Bit
15-8
7-0
LOOP
0
1
1
1
Name
Name
IADR
IADR
DRX
DTX
RES
INTL
X
0
1
1
MENDECL
X
X
0
1
Read/write accessible only when
STOP bit is set. LOOP is cleared
by RESET.
Disable Transmit. If this bit is set,
the PCnet-ISA
access the Transmit Descriptor
Ring and, therefore, no transmis-
sions will occur. DTX = “0” will set
TXON bit (CSR0.4) after STRT
(CSR0.1) is asserted. DTX is de-
fined after the initialization block
is read.
Read/write accessible only when
STOP bit is set.
Disable Receiver. If this bit is set,
the PCnet-ISA
access the Receive Descriptor
Ring and, therefore, all receive
frame data are ignored. DRX =
“0” will set RXON bit (CSR0.5) af-
ter STRT (CSR0.1) is asserted.
DRX is defined after the initializa-
tion block is read.
Read/write accessible only when
STOP bit is set.
Lower 16 bits of the address of
the Initialization Block. Bit loca-
tion 0 must be zero. This register
is an alias of CSR1. Whenever
this register is written, CSR1 is
updated with CSR16’s contents.
Read/Write
when the STOP bit in CSR0 is
set. Unaffected by RESET.
Reserved locations. Written as
zero and read as undefined.
Upper 8 bits of the address of the
Initialization Block. Bit locations
15-8 must be written with zeros.
Non-loopback
External Loopback
Internal Loopback Include
MENDEC
Internal Loopback Exclude
MENDEC
Loopback Mode
Description
Description
+
+
accessible
controller will not
controller will not
P R E L I M I N A R Y
only
Am79C961
CSR18-19: Current Receive Buffer Address
Bit
31-24
23-0
CSR20-21: Current Transmit Buffer Address
Bit
31-24
23-0
CSR22-23: Next Receive Buffer Address
Bit
31-24
23-0
CSR24-25: Base Address of Receive Ring
Bit
31-24
23-0
CRBA
NRBA
BADR
CXBA
Name
Name
Name
Name
RES
RES
RES
RES
This register is an alias of CSR2.
Whenever this register is written,
CSR2 is updated with CSR17’s
contents.
Read/Write
when the STOP bit in CSR0 is
set. Unaffected by RESET.
Reserved locations. Written as
zero and read as undefined.
Contains the current receive
buffer address to which the
PCnet-ISA
incoming frame data.
Read/write accessible only when
STOP bit is set.
Reserved locations. Written as
zero and read as undefined.
Contains the current transmit
buffer address from which the
PCnet-ISA
ting.
Read/write accessible only when
STOP bit is set.
Reserved locations. Written as
zero and read as undefined.
Contains the next receive buffer
address to which the PCnet-ISA
controller will store incoming
frame data.
Read/write accessible only when
STOP bit is set.
Reserved locations. Written as
zero and read as undefined.
Contains the base address of the
Receive Ring.
Read/write accessible only when
STOP bit is set.
Description
Description
Description
Description
+
+
controller is transmit-
controller will store
accessible
AMD
1-557
only
+