am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 87

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

CSR72: Receive Ring Counter
Bit
15-0
CSR74: Transmit Ring Counter
Bit
15-0
CSR76: Receive Ring Length
Bit
15-0
CSR78: Transmit Ring Length
Bit
15-0
RCVRC
XMTRC
RCVRL
XMTRL
Name
Name
Name
Name
Receive Ring Counter location.
Contains a Two’s complement
binary number used to number
the current receive descriptor.
This counter interprets the value
in CSR76 as pointing to the first
descriptor; a two’s complement
value of -1 (FFFFh) corresponds
to the last descriptor in the ring.
Read/write accessible only when
STOP bit is set.
Transmit Ring Counter location.
Contains a Two’s complement
binary number used to number
the current transmit descriptor.
This counter interprets the value
in CSR78 as pointing to the first
descriptor; a two’s complement
value of -1 (FFFFh) corresponds
to the last descriptor in the ring.
Read/write accessible only when
STOP bit is set.
Receive Ring Length. Contains
the Two’s complement of the re-
ceive descriptor ring length. This
register is initialized during the
PCnet-ISA
tion routine based on the value in
the RLEN field of the initialization
block. This register can be manu-
ally altered; the actual receive
ring length is defined by the cur-
rent value in this register.
Read/write accessible only when
STOP bit is set.
Transmit Ring Length. Contains
the two’s complement of the
transmit descriptor ring length.
This register is initialized during
the
initialization routine based on the
value in the TLEN field of the
initialization block. This register
PCnet-ISA
Description
Description
Description
Description
+
controller initializa-
+
controller
P R E L I M I N A R Y
Am79C961
CSR80: Burst and FIFO Threshold Control
Bit
15-14
13-12RCVFW[1:0]
11-10XMTSP[1:0]
RCVFW[1:0]
Name
RES
00
01
10
11
can be manually altered; the ac-
tual transmit ring length is
defined by the current value in
this register.
Read/write accessible only when
STOP bit is set.
Reserved locations. Read as
ones. Written as zero.
Receive
RCVFW controls the point at
which ISA bus receive DMA is re-
quested in relation to the number
of received bytes in the receive
FIFO. RCVFW specifies the
number of bytes which must be
present (once the frame has
been verified as a non-runt) be-
fore receive DMA is requested.
Note however that in order for re-
ceive DMA to be performed for a
new frame, at least 64 bytes must
have been received. This effec-
tively avoids having to react to
receive frames which are runts or
suffer a collision during the slot
time (512 bit times). If the Runt
Packet Accept feature is en-
abled, receive DMA will be
requested as soon as either the
RCVFW threshold is reached, or
a complete valid receive frame is
detected (regardless of length).
RCVFW is set to a value of 10b
(64 bytes) after RESET.
Read/write accessible only when
STOP bit is set.
Transmit Start Point. XMTSP
controls the point at which pre-
amble
commence in relation to the num-
ber of bytes written to the
transmit FIFO for the current
transmit frame. When the entire
frame is in the FIFO, transmis-
sion will start regardless of the
value in XMTSP. XMTSP is given
a value of 10b (64 bytes) after
RESET. Regardless of XMTSP,
the FIFO will not internally over
transmission
Description
FIFO
Bytes Received
Reserved
16
32
64
Watermark.
AMD
attempts
1-561