am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 62

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

General Purpose Serial Interface (GPSI)
The PCnet-ISA
Serial Interface (GPSI) designed for testing the digital
portions of the chip. The MENDEC, AUI, and twisted
pair interface are by-passed once the device is set up in
the special “test mode” for accessing the GPSI func-
tions. Although this access is intended only for testing
the device, some users may find the non-encoded data
functions useful in some special applications. Note,
however, that the GPSI functions can be accessed only
when the PCnet-ISA
The PCnet-ISA
LANCE digital serial interface. Since the GPSI functions
can be accessed only through a special test mode, ex-
pect some loss of functionality to the device when the
GPSI is invoked. The AUI and 10BASE-T analog inter-
faces are disabled along with the internal MENDEC
logic. The LA (unlatched address) pins are removed and
become the GPSI signals, therefore, only 20 bits of ad-
dress space is available. The table below shows the
GPSI pin configuration:
1-536
Note:
The GPSI Function is available only in the Bus Master Mode of operation.
Receive Data
Receive Clock
Receive Carrier Sense
Collision
Transmit Clock
Transmit Enable
Transmit Data
AMD
Function
GPSI
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controller contains a General Purpose
GPSI signals are consistent with the
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devices operate as a bus master.
I/O Type
GPSI
O
O
I
I
I
I
I
GPSI Pin Configurations
GPSI Pin
LANCE
P R E L I M I N A R Y
RENA
RCLK
CLSN
TENA
TCLK
RX
TX
Am79C961
PCnet-ISA
GPSI Pin
SRDCLK
To invoke the GPSI signals, follow the procedure below:
1. After reset or I/O read of Reset Address, write 10b
2. Set the ENTST bit in CSR4
3. Set the GPSIEN bit in CSR124 (see note below)
(The pins LA17–LA23 will change function after the
completion of the above three steps.)
4. Clear the ENTST bit in CSR4
5. Clear Media Select bits in ISACSR2
6. Define the PORTSEL bits in the MODE register
Note: LA pins will be tristated before writing to GPSIEN
bit. After writing to GPSIEN, LA[17–21] will be inputs,
LA[22–23] will be outputs.
STDCLK
RXCRS
RXDAT
TXDAT
CLSN
TXEN
to PORTSEL bits in CSR15.
(CSR15) to be 10b to define GPSI port. The
MODE register image is in the initialization block.
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Pin Number
PCnet-ISA
10
11
12
5
6
7
9
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Normal Pin Function
PCnet-ISA
LA17
LA18
LA19
LA20
LA21
LA22
LA23
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