am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 79

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

14
13
12
11 APAD_XMT
10 ASTRP_RCV
9
DMAPLUS
DPOLL
TIMER
MFCO
register test functions are en-
abled. In order to set ENTST, it
must be written with a “1” during
the first write access to CSR4
after RESET. Once a “0” is
written to this bit location, ENTST
cannot be set until after the
PCnet-ISA
ENTST is cleared by RESET.
When DMAPLUS = “1” , the burst
transaction counter in CSR80 is
disabled. If DMAPLUS = “0”, the
burst transaction counter is
enabled.
DMA-PLUS
RESET.
Timer Enable Register. If TIMER
is set, the Bus Timer Register,
CSR82, is enabled. If TIMER is
set, CSR82 must be written with
a value. If TIMER is cleared, the
Bus Timer Register is disabled.
TIMER is cleared by RESET.
Disable
DPOLL is set, the Buffer Man-
agement
transmit polling. Likewise, if
DPOLL is cleared, automatic
transmit polling is enabled. If
DPOLL is set, TDMD bit in CSR0
must be periodically set in order
to initiate a manual poll of a trans-
mit descriptor. Transmit descrip-
tor polling will not take place if
TXON is reset.
DPOLL is cleared by RESET.
Auto Pad Transmit. When set,
APAD_XMT enables the auto-
matic padding feature. Transmit
frames will be padded to extend
them to 64 bytes, including FCS.
The FCS is calculated for the en-
tire frame (including pad) and
appended after the pad field.
APAD_XMT will override the pro-
gramming of the DXMTFCS bit
(CSR15.3).
APAD_ XMT is reset by activa-
tion of the RESET pin.
ASTRP_RCV enables the auto-
matic pad stripping feature. The
pad and FCS fields will be
stripped from receive frames and
not placed in the FIFO.
ASTRP_ RCV is reset by activa-
tion of the RESET pin.
Missed Frame Counter Overflow
Interrupt.
Transmit
+
Unit
controller is reset.
is
will
cleared
Polling.
P R E L I M I N A R Y
disable
Am79C961
by
If
8
7-6
5
4
3
2
1
RCVCCOM
TXSTRTM
RCVCCO
TXSTRT
MFCOM
RES
JAB
This bit indicates the MFC
(CSR112) has overflowed. Can
be cleared by writing a “1” to this
bit. Also cleared by RESET or
setting the STOP bit. Writing a “0”
has no effect.
Missed Frame Counter Overflow
Mask.
If MFCOM is set, MFCO will not
set INTR in CSR0.
MFCOM is set by Reset and is
not affected by STOP.
Reserved locations. Read and
written as zero.
Receive Collision Counter Over-
flow.
This bit indicates the Receive
Collision Counter (CSR114) has
overflowed. It can be cleared by
writing a 1 to this bit. Also cleared
by RESET or setting the STOP
bit. Writing a 0 has no effect.
Receive Collision Counter Over-
flow Mask.
If RCVCCOM is set, RCVCCO
will not set INTR in CSR0.
RCVCCOM is set by RESET and
is not affected by STOP.
Transmit Start status is set when-
ever
begins trans- mission of a frame.
When TXSTRT is set, IRQ is as-
serted if IENA = 1 and the mask
bit TXSTRTM (CSR4.2) is clear.
TXSTRT is set by the MAC Unit
and cleared by writing a “1”, set-
ting RESET or setting the STOP
bit. Writing a “0” has no effect.
Transmit
TXSTRTM is set, the TXSTRT bit
in CSR4 will be masked and will
not set INTR flag in CSR0.
TXS-TRTM is set by RESET and
is not affected by STOP.
Jabber Error is set when the
PCnet-ISA
pair MAU function exceeds an
allowed transmission limit. Jab-
ber is set by the TMAU cell and
can
10BASE-T mode.
When JAB is set, IRQ is asserted
if IENA = 1 and the mask bit
JABM (CSR4.4) is clear.
only
PCnet-ISA
+
Start
controller Twisted-
be
+
asserted
Mask.
AMD
controller
1-553
in
If