am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 163

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

SETUP:
The driver should set up descriptors in groups of 3, with
the OWN and STP bits of each set of three descriptors to
read as follows: 11b, 10b, 00b.
An option bit (LAPPEN) exists in CSR3, bit position 5.
The software should set this bit. When set, the LAPPEN
bit directs the PCnet-ISA
when STP has been written to a receive descriptor by
the PCnet-ISA
FLOW:
The PCnet-ISA
scriptor at some point in time before a message arrives.
The PCnet-ISA
buffer is OWNed by the PCnet-ISA
stores the descriptor information to be used when a
message does arrive.
N0: Frame preamble appears on the wire, followed by
N1: The 64th byte of frame data arrives from the wire.
C0: When the 64th byte of the message arrives, the
C1: The PCnet-ISA
S0: The driver remains idle.
C2: When the PCnet-ISA
C3: When the first descriptor for the frame has been
S1: The SRP INTERRUPT causes the CPU to switch
C4: During the CPU interrupt-generated task switch-
SFD and destination address.
This causes the PCnet-ISA
frame data DMA operations to the first buffer.
PCnet-ISA
eration to the next receive descriptor. This descrip-
tor should be owned by the PCnet-ISA
the bus to transfer frame data to the first buffer as it
arrives on the wire.
filled the first buffer, it writes status to the first
descriptor.
written, changing ownership from the PCnet-ISA
controller to the CPU, the PCnet-ISA
generate an SRP INTERRUPT. (This interrupt ap-
pears as a RINT interrupt in CSR0.)
tasks to allow the PCnet-ISA
run.
ing, the PCnet-ISA
lookahead operation to the third descriptor. At this
point in time, the third descriptor is owned by the
CPU. [ Note: Even though the third buffer is not
owned by the PCnet-ISA
Ethernet controllers will continue to perform data
DMA into the buffer space that the controller al-
ready owns (i.e. buffer number 2). The controller
does not know if buffer space in buffer number 2
will be sufficient or not, for this frame, but it has no
way to tell except by trying to move the entire
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controller.
controller polls the current receive de-
controller determines that this receive
controller performs a lookahead op-
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controller intermittently requests
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to generate an INTERRUPT
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controller is performing a
controller has completely
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controller, existing AMD
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controller’s driver to
controller to begin
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controller and it
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controller will
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controller.
Am79C961
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S2: The first task of the driver’s interrupt service routine
S3: The application will return an application buffer
C5: Interleaved with S2, S3 and S4 driver activity, the
S4: The driver will next proceed to copy the contents of
S5: After copying all of the data from the first buffer into
C6: At this point, knowing that it had not previously
C7: After filling the second buffer and performing the
S6: After the ownership of descriptor number 2 has
message into that space. Only when the message
does not fit will it signal a buffer error condition—
there is no need to panic at the point that it discov-
ers that it does not yet own descriptor number 3. ]
is to collect the header information from the
PCnet-ISA
the application.
pointer to the driver. The driver will add an offset to
the application data buffer pointer, since the
PCnet-ISA
tion of the message into the first and second buff-
ers. (The modified application data buffer pointer
will only be directly used by the PCnet-ISA
ler when it reaches the third buffer.) The driver will
place the modified data buffer pointer into the final
descriptor of the group (#3) and will grant owner-
ship of this descriptor to the PCnet-ISA
PCnet-ISA
number 2.
the PCnet-ISA
ning of the application space. This copy will be to
the exact (unmodified) buffer pointer that was
passed by the application.
the beginning of the application data buffer, the
driver will begin to poll the ownership bit of the sec-
ond descriptor. The driver is waiting for the PCnet-
ISA
owned the third descriptor, and knowing that the
current message has not ended (there is more data
in the fifo), the PCnet-ISA
“last ditch lookahead” to the final (third) descriptor;
This time, the ownership will be TRUE (i.e. the de-
scriptor belongs to the controller), because the
driver wrote the application pointer into this de-
scriptor and then changed the ownership to give
the descriptor to the PCnet-ISA
S3. Note that if steps S1, S2 and S3 have not com-
pleted at this time, a BUFF error will result.
last chance lookahead to the next descriptor, the
PCnet-ISA
change the ownership bit of descriptor number 2.
been changed by the PCnet-ISA
next driver poll of the 2nd descriptor will show
ownership granted to the CPU. The driver now
copies the data from buffer number 2 into the “mid-
dle section” of the application buffer space. This
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controller to finish filling the second buffer.
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controller will write frame data to buffer
controller will be placing the first por-
controller’s first buffer and pass it to
controller will write the status and
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controller’s first buffer to the begin-
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controller will make a
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controller back at
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controller, the
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AMD
controller.
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control-
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