am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 67

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

The following signals are not driven by the Permanent
Master and are simply pulled HIGH: BALE, IOCHRDY,
IOCS16, MEMCS16, SRDY. Therefore, the PCnet-ISA
controller assumes the memory which it is accessing is
16 bits wide and can complete an access in the time pro-
grammed for the PCnet-ISA
MEMW signals. Refer to the ISA Bus Configuration
Register description section.
Release Phase
When the PCnet-ISA
it drives the command lines inactive. 50 ns later, the con-
troller tri-states the command, address, and data lines
and drives DRQ inactive. 50 ns later, the controller
drives MASTER inactive.
The Permanent Master drives AEN active within 71 ns of
MASTER going inactive. The Permanent Master is al-
lowed to drive the command lines no sooner than 60 ns
after DACK goes inactive.
Master Mode Memory Read Cycle
After the PCnet-ISA
bus, it can perform a memory read cycle. All timing is
generated relative to the 20 MHz clock (network clock).
Since there is no way to tell if memory is 8- or 16-bit or
when it is ready, the PCnet-ISA
sumes 16-bit, 1 wait state memory. The wait state
assumption is based on the default value in the MSRDA
register in ISACSR0.
The cycle begins with SA0-19, SBHE, and LA17-23 be-
ing presented. The ISA bus requires them to be valid for
at least 28 ns before a read command and the
PCnet-ISA
setup time before asserting MEMR.
The ISA bus requires MEMR to be active for at least
219 ns, and the PCnet-ISA
of 5 clocks, or 250 ns, but this can be tuned for faster
systems with the Master Mode Read Active (MSRDA)
register (see section 2.5.2). Also, if IOCHRDY is driven
LOW, the PCnet-ISA
counter must expire and IOCHRDY must be HIGH for
the PCnet-ISA
The PCnet-ISA
read data. The ISA bus requires all command lines to re-
main inactive for at least 97 ns before starting another
bus cycle and the PCnet-ISA
least two clocks or 100 ns of inactive time.
The ISA bus requires read data to be valid no more than
173 ns after receiving MEMR active and the PCnet-
ISA+ controller requires 10 ns of data setup time. The
ISA bus requires read data to provide at least 0 ns of
hold time and to be removed from the bus within 30 ns
after MEMR goes inactive. The PCnet-ISA
requires 0 ns of data hold time.
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controller provides one clock or 50 ns of
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controller to continue.
controller then accepts the memory
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controller is finished with the bus,
controller will wait. The wait state
controller has acquired the ISA
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controller provides a default
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controller by default as-
controller MEMR and
controller provides at
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controller
P R E L I M I N A R Y
Am79C961
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Master Mode Memory Write Cycle
After the PCnet-ISA
bus, it can perform a memory write cycle. All timing is
generated relative to a 20 MHz clock which happens to
be the same as the network clock. Since there is no way
to tell if memory is 8- or 16-bit or when it is ready, the
PCnet-ISA
state memory. The wait state assumption is based on
the default value in the MSWRA register in ISACSR1.
The cycle begins with SA0-19, SBHE, and LA17-23 be-
ing presented. The ISA bus requires them to be valid at
least 28 ns before MEMW goes active and data to be
valid at least 22 ns before MEMW goes active. The
PCnet-ISA
setup time for all these signals.
The ISA bus requires MEMW to be active for at least
219 ns, and the PCnet-ISA
of 5 clocks, or 250 ns, but this can be tuned for faster
systems with the Master Mode Write Active (MSWRA)
register (ISACSR1). Also, if IOCHRDY is driven LOW,
the PCnet-ISA
HIGH for the PCnet-ISA
The ISA bus requires data to be valid for at least 25 ns
after MEMW goes inactive, and the PCnet-ISA
ler provides one clock or 50 ns.
The ISA bus requires all command lines to remain inac-
tive for at least 97 ns before starting another bus cycle.
The PCnet-ISA
or 100 ns of inactive time when bit 4 in ISACSR2 is set.
The EISA bus requires all command lines to remain in-
active for at least 170 ns before starting another bus
cycle. When bit 4 in ISACSR4 is cleared, the
PCnet-ISA
Shared Memory Mode
Address PROM Cycles External PROM
The Address PROM is a small (16 bytes) 8-bit PROM
connected to the PCnet-ISA
Bus (PRDB). The PCnet-ISA
only 8-bit ISA I/O bus cycles for the address PROM; this
limitation is transparent to software and does not pre-
clude 16-bit software I/O accesses. An access cycle
begins with the Permanent Master driving AEN LOW,
driving the addresses valid, and driving IOR active. The
PCnet-ISA
nals and arbitrates for the Private Data Bus if necessary.
IOCHRDY is always driven LOW during address PROM
accesses.
When the Private Data Bus becomes available, the
PCnet-ISA
IOCHRDY, turns on the data path from PRD0-7, and en-
ables the SD0-7 drivers (but not SD8-15). During this
bus cycle, IOCS16 is not driven active. This condition is
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controller by default assumes 16-bit, 1 wait
controller provides 200 ns of inactive time.
controller detects this combination of sig-
controller provides one clock or 50 ns of
controller drives APCS active, releases
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controller will wait. IOCHRDY must be
controller provides at least two clocks
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controller has acquired the ISA
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controller to continue.
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controller provides a default
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controller Private Data
controller will support
AMD
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control-
1-541