am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 82

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

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*Refer to the section on General Purpose Serial Interface for
detailed information on accessing GPSI.
AMD
PORTSEL
PORTSEL[1:0]
DRTY
TSEL
INTL
[1:0]
0 0
0 1
1 0
1 1
Read/write accessible only when
STOP bit is set. Cleared by
RESET.
Transmit Mode Select. TSEL
controls the levels at which the
AUI drivers rest when the AUI
transmit port is idle. When TSEL
= 0, DO+ and DO- yield “zero” dif-
ferential to operate transformer
coupled loads (Ethernet 2 and
802.3). When TSEL = 1, the DO+
idles at a higher value with re-
spect to DO- , yielding a logical
HIGH state (Ethernet 1).
This bit only has meaning when
the AUI network interface is
selected. Not available under
Auto-Select Mode.
Read/write accessible only when
STOP bit is set. Cleared by
RESET.
Port Select bits allow for software
controlled selection of the net-
work medium. PORTSEL active
only when Media-Select Bit set to
0 in ISACSR2.
Read/write accessible only when
STOP bit is set. Cleared by
RESET.
The network port configuration
are as follows:
Internal Loopback. See the de-
scription of LOOP, CSR15.2.
Read/write accessible only when
STOP bit is set.
Disable Retry. When DRTY = “1”,
PCnet-ISA
tempt only one transmission. If
DRTY = “0”, PCnet-ISA
ler will attempt to transmit 16
times before signaling a retry
error.
Read/write accessible only when
STOP bit is set.
+
Network Port
controller will at-
10BASE-T
Reserved
GPSI*
AUI
P R E L I M I N A R Y
+
control-
Am79C961
4
3
2
DXMTFCS
FCOLL
LOOP
Force Collision. This bit allows
the collision logic to be tested.
PCnet-ISA
internal loopback for FCOLL to
be valid. If FCOLL = “1”, a colli-
sion
loopback transmission attempts;
a Retry Error will ultimately re-
sult. If FCOLL = “0”, the Force
Collision logic will be disabled.
Read/write accessible only when
STOP bit is set.
Disable Transmit CRC (FCS).
When DXMTFCS = 0, the trans-
mitter will generate and append a
FCS to the transmitted frame.
When DXMTFCS = 1, the FCS
logic is allocated to the receiver
and no FCS is generated or sent
with the transmitted frame.
See also the ADD_FCS bit in
TMD1. If DXMTFCS is set, no
FCS will be generated. If both
DXMTFCS is set and ADD_FCS
is clear for a particular frame, no
FCS
ADD_FCS is set for a particular
frame, the state of DXMTFCS is
ignored and a FCS will be ap-
pended on that frame by the
transmit circuitry.
In loopback mode, this bit deter-
mines if the transmitter appends
FCS or if the receiver checks the
FCS.
This bit was called DTCR in the
LANCE (Am7990).
Read/write accessible only when
STOP bit is set.
Loopback
PCnet-ISA
in full duplex mode for test pur-
poses. When LOOP = “1”,
loopback is enabled. In combina-
tion with INTL and MENDECL,
various loopback modes are de-
fined as follows:
will
will
+
+
controller must be in
controller to operate
be
be
Enable
forced
generated. If
during
allows