am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 57

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

controller and Internal Transmit Enable (ITXEN). The in-
ternal transmit clock is also used as a stable bit-rate
clock by the receive section of the MENDEC and con-
troller.
The oscillator requires an external 0.005% crystal, or an
external 0.01% CMOS-level input as a reference. The
accuracy requirements, if an external crystal is used,
are tighter because allowance for the on-chip oscillator
must be made to deliver a final accuracy of 0.01%.
Transmission is enabled by the controller. As long as the
ITXEN request remains active, the serial output of the
controller will be Manchester encoded and appear at
DO . When the internal request is dropped by the con-
troller, the differential transmit outputs go to one of two
idle states, dependent on TSEL in the Mode Register
(CSR15, bit 9):
Receive Path
The principal functions of the receiver are to signal the
PCnet-ISA
ceive pair, and to separate the incoming Manchester
encoded data stream into clock and NRZ data.
The receiver section (see Receiver Block Diagram) con-
sists of two parallel paths. The receive data path is a
zero threshold, wide bandwidth line receiver. The carrier
path is an offset threshold bandpass detecting line re-
ceiver. Both receivers share common bias networks to
allow operation over a wide input common mode range.
Input Signal Conditioning
Transient noise pulses at the input data stream are re-
jected by the Noise Rejection Filter. Pulse width
rejection is proportional to transmit data rate which is
fixed at 10 MHz for Ethernet systems but which could be
different for proprietary networks. DC inputs more nega-
tive than minus 100 mV are also suppressed.
TSEL LOW:
TSEL HIGH:
+
controller that there is information on the re-
DI
The idle state of DO yields “zero”
differential to operate transformer-
coupled loads.
In this idle state, DO+ is positive
with respect to DO– (logical HIGH).
*Internal signal
Receiver
Reject
Noise
Data
Filter
Receiver Block Diagram
P R E L I M I N A R Y
Am79C961
The Carrier Detection circuitry detects the presence of
an incoming data packet by discerning and rejecting
noise from expected Manchester data, and controls the
stop and start of the phase-lock loop during clock acqui-
sition. Clock acquisition requires a valid Manchester bit
pattern of 1010b to lock onto the incoming message.
When input amplitude and pulse width conditions are
met at DI , a clock acquisition cycle is initiated.
Clock Acquisition
When there is no activity at DI (receiver is idle), the re-
ceive oscillator is phase-locked to STDCLK. The first
negative clock transition (bit cell center of first valid
Manchester “0”) after clock acquisition begins interrupts
the receive oscillator. The oscillator is then restarted at
the second Manchester “0” (bit time 4) and is phase-
locked to it. As a result, the MENDEC acquires the clock
from the incoming Manchester bit pattern in 4 bit times
with a “1010” Manchester bit pattern.
The internal receiver clock, IRXCLK, and the internal re-
ceived data, IRXDAT, are enabled 1/4 bit time after
clock acquisition in bit cell 5. IRXDAT is at a HIGH state
when the receiver is idle (no IRXCLK). IRXDAT how-
ever, is undefined when clock is acquired and may
remain HIGH or change to LOW state whenever
IRXCLK is enabled. At 1/4 bit time through bit cell 5, the
controller portion of the PCnet-ISA
first IRXCLK transition. This also strobes in the incoming
fifth bit to the MENDEC as Manchester “1”. IRXDAT
may make a transition after the IRXCLK rising edge in bit
cell 5, but its state is still undefined. The Manchester “1”
at bit 5 is clocked to IRXDAT output at 1/4 bit time in bit
cell 6.
PLL Tracking
After clock acquisition, the phase-locked clock is com-
pared to the incoming transition at the bit cell center
(BCC) and the resulting phase error is applied to a cor-
rection
phase-locked clock remains locked on the received sig-
nal. Individual bit cell phase corrections of the Voltage
Controlled Oscillator (VCO) are limited to 10% of the
phase
locked clock.
Manchester
difference
circuit.
Decoder
Carrier
Detect
Circuit
This
between
circuit
18183B-15
BCC
IRXDAT*
IRXCLK*
IRXCRS*
16907B-8
ensures
+
controller sees the
and
AMD
that
phase-
1-531
the