am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 45

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

DMA[2:0]
BPAM[3:0]
BP_16B
BPSZ[3:0]
DMA[2:0]
0
1
1
1
BPAM[3:0]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DMA Channel (DRQ/DACK Pair)
Channel 3
Channel 5
Channel 6
Channel 7
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Address
Location (Hex)
C0000
C2000
C4000
C6000
C8000
CA000
CC000
CE000
D0000
D2000
D4000
D6000
D8000
DA000
DC000
DE000
DMA
0x74). Controls the DRQ and
DMA selection of PCnet-ISA
The DMA[2:0] register will be
written with a value from the
EEPROM.
Mode Only} The DRQ signal will
not be driven unless EE_VALID
is set or Non-EEPROM sequen-
tial write process is complete.
Boot PROM Address Match to
bits [23:16] of SA bus (PnP
0x40–0x41). Selects the location
where the Boot PROM Address
match decode is started. The
BPAM will be written with a value
from the EEPROM.
Boot PROM 16-bit access (PnP
0x42). Is asserted if Boot PROM
cycles should respond as an
16-bit device. In Bus Master
mode, all boot PROM cycles will
only be 8 bits in width.
Boot
0x43–0x44). Selects the size of
the boot PROM selected.
Channel
PROM
{For Bus Master
Size Supported
(K bytes)
8, 16, 32, 64
8
8, 16
8
8, 16, 32
8
8, 16
8
8, 16, 32, 64
8
8, 16
8
8, 16, 32
8
8, 16
8
Select
Size
P R E L I M I N A R Y
(PnP
(PnP
Am79C961
+
.
SRAM[3:0]
SR_16B
SRSZ[3:0]
Vendor Defined Byte (PnP 0x0F)
IO_MODE
BPSZ[3:0]
0
1
1
1
1
SRAM[2:0]
0
0
0
0
1
1
1
1
SRSZ[3:0]
0
1
1
1
1
x
1
1
1
0
0
0
1
1
0
0
1
1
x
1
1
1
0
x
1
1
0
0
0
1
0
1
0
1
0
1
x
1
1
0
0
x
1
0
0
0
x
1
0
0
0
Boot PROM Size
No Boot PROM Selected
8 K
16 K
32 K
64 K
SA[15:13]
0
0
0
0
1
1
1
1
Shared Memory Size
No Static RAM Selected
8 K
16 K
32 K
64 K
0
0
1
1
0
0
1
1
Static RAM Address Match to
bits [16:13] of SA bus (PnP
0x48–0x49). Selects the starting
location of the Shared memory
by using SA[16:13] for perform-
ing address comparisons. The
shared memory address match,
the SMAM is asserted low.
SRAM[3] value must reflect the
external address match logic for
SA[16].
Static RAM 16-bit access (PnP
0x4A). Asserted if SRAM cycles
should respond as an 16-bit
device.
Static RAM Size (PnP 0x4B–
0x4C). Selects the size of the
static RAM selected.
I/O Mode. When set to one, the
internal selection will respond as
a 16-bit port, (i.e. drive IOCS16
pin). When IO_MODE is set to
zero, (Default), the internal I/O
0
1
0
1
0
1
0
1
SRAM Size
(K bytes)
8, 16, 32, 64
8
8, 16
8
8, 16, 32
8
8, 16
8
AMD
1-519