am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 81

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

CSR13: Physical Address Register, PADR[31:16]
Bit
15-0 PADR[31:16]
CSR14: Physical Address Register, PADR[47:32]
Bit
15-0 PADR[47:32]
CSR15: Mode Register
Bit
15
14
13
DRCVBC
DRCVPA
PROM
Name
Name
Name
Physical
PADR[31:16]. Undefined until in-
itialized either automatically by
loading the initialization block or
directly by an I/O write to this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
Read/write accessible only when
STOP bit is set.
Physical
PADR[47:32]. Undefined until in-
itialized either automatically by
loading the initialization block or
directly by an I/O write to this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
Read/write accessible only when
STOP bit is set.
This register’s fields are loaded
during the PCnet-ISA
initialization routine with the cor-
responding Initialization Block
values. The register can also be
loaded directly by an I/O write.
Activating the RESET pin clears
all bits of CSR15 to zero.
Promiscuous Mode.
When PROM = “1”, all incoming
receive frames are accepted.
Read/write accessible only when
STOP bit is set.
DisableReceive Broadcast
set, disables the PCnet-ISA
controller from receiving broad-
cast
protocols that do not support
broadcast addressing, except as
a function of multicast. DRCVBC
is cleared by activation of the
RESET pin (broadcast mes-
sages will be received).
Read/write accessible only when
STOP bit is set.
Disable Receive Physical Ad-
dress. When set, the physical
address detection (Station or
messages.
Description
Description
Description
Address
Address
Used
+
controller
P R E L I M I N A R Y
Register,
Register,
.
When
Am79C961
for
+
12
11
10
9
MENDECL
LRT/TSEL
DLNKTST
DAPC
LRT
node ID) of the PCnet-ISA
troller will be disabled. Frames
addressed to the nodes individ-
ual physical address will not be
recognized (although the frame
may be accepted by the EADI
mechanism).
Read/write accessible only when
STOP bit is set.
Disable
DLNKTST = “1”, monitoring of
Link Pulses is disabled. When
DLNKTST = “0”, monitoring of
Link Pulses is enabled. This bit
only has meaning when the
10BASE-T network interface is
selected.
Read/write accessible only when
STOP bit is set.
Disable Automatic Polarity Cor-
rection. When DAPC = “1”, the
10BASE-T receive polarity rever-
sal
Likewise, when DAPC = “0”, the
polarity reversal algorithm is en-
abled.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Read/write accessible only when
STOP bit is set.
MENDEC Loopback Mode. See
the description of the LOOP bit in
CSR15.
Read/write accessible only when
STOP bit is set.
Low Receive Threshold (T-MAU
Mode only)
Transmit Mode Select (AUI
Mode only)
Low Receive Threshold. When
LRT = “1”, the internal twisted
pair receive thresholds are re-
duced by 4.5 dB below the
standard 10BASE-T value (ap-
proximately
unsquelch threshold for the RXD
circuit will be 180-312 mV peak.
When LRT = “0”, the unsquelch
threshold for the RXD circuit will
be
value, 300-520 mV peak.
In either case, the RXD circuit
post squelch threshold will be
one
threshold.
This bit only has meaning when
the 10BASE-T network interface
is selected.
the
algorithm
half
Link
standard
of
3/5)
the
Status.
is
10BASE-T
and
unsquelch
AMD
disabled.
+
When
1-555
con-
the