am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 47

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

Use Without EEPROM
In some designs, especially PC motherboard applica-
tions, it may be desirable to eliminate the EEPROM
altogether. This would save money, space, and power
consumption.
The operation of this mode is similar to when the
PCnet-ISA
cept that to enter this mode the SHFBUSY pin is left
unconnected. The device will enter software relocatable
mode, and the BIOS on the motherboard can wake up
the device, configure it, load the IEEE address (possibly
stored in Flash ROM) into the PCnet-ISA
and activate the device.
External Scan Chain
The External Scan Chain is a set of bits stored in the
EEPROM which are not used in the PCnet-ISA
ler but which can be used with external hardware to
allow jumperless configuration of external devices.
After RESET, the PCnet-ISA
the EEPROM and storing the information in registers in-
side the PCnet-ISA
during the read of the EEPROM. If external circuitry is
added, such as a shift register, which is clocked from
SCLK and is attached to DO from the EEPROM, data
read out of the EEPROM will be shifted into the shift reg-
ister. After reading the EEPROM to the end of the
External Shift Chain, and if there is a correct checksum,
SHFBUSY will go low. This will be used to latch the infor-
mation from the EEPROM into the shift register. If the
checksum is invalid, SHFBUSY will not go low, indicat-
ing that the EEPROM may be bad.
For more information on the use of this function, please
refer to the technical reference manual.
Flash PROM
Use
Instead of using a PROM or EPROM for the Boot
PROM, it may be desirable to use a Flash or EEPROM
type of device for storing the Boot code. This would al-
low for in-system updates and changes to the
information in the Boot ROM without opening up the PC.
It may also be desirable to store statistics or drivers in
the Flash device.
Interface
To use a Flash-type device with the PCnet-ISA
ler, Flash Select is set in register 0F0h of the Plug and
Play registers. Flash Select is cleared by RESET (de-
fault).
In bus master mode, BPCS becomes Flash_OE and
IRQ12 becomes Flash_WE. The Flash ROM devices
CS pin is connected to ground.
In shared memory mode, BPCS becomes Flash_ CS
and IRQ12 becomes the static RAM Chip Select, and
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controller encounters a checksum error, ex-
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controller. SHFBUSY is held high
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controller begins reading
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controller,
P R E L I M I N A R Y
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control-
control-
Am79C961
the SROE and SRWE signals are connected to both the
SRAM and Flash devices.
Optional IEEE Address PROM
Normally, the Ethernet physical address will be stored in
the EEPROM with the other configuration data. This re-
duces the parts count, board space requirements, and
power consumption. The option to use a standard
parallel 8 bit PROM is provided to manufactures who are
concerned about the non-volatile nature of EEPROMs.
To use a 8 bit parallel prom to store the IEEE address
data instead of storing it in the EEPROM, the
APROM_EN bit is set in the Plug and Play registers by
the EEPROM upon RESET. IRQ15 is redefined by the
setting of this bit to be APCS, or ADDRESS PROM
CHIP SELECT. This pin is connected to an external 8 bit
PROM, such as a 27LS19. The address pins of the
PROM are connected to the lower address pins of the
ISA bus, and the data lines are connected to the private
data bus.
In this mode, any accesses to the IEEE address will be
passed to the external PROM and the data will be
passed through the PCnet-ISA
data bus.
EISA Configuration Registers
The PCnet-ISA
EISA Configuration Registers. These are used in EISA
systems to identify the card and load the appropriate
configuration file for that card. This feature is enabled
using bit 10 of ISACSR2. When set to 1, the EISA Con-
figuration registers will be enabled and will be read at I/O
location 0xC80-0xC83. The contents of these 4 regis-
ters are stored in the EEPROM and are automatically
read in at RESET.
Bus Interface Unit (BIU)
The bus interface unit is a mixture of a 20 MHz state ma-
chine and asynchronous logic. It handles two types of
accesses; accesses where the PCnet-ISA
a slave and accesses where the PCnet-ISA
the Current Master.
In slave mode, signals like IOCS16 are asserted and
deasserted as soon as the appropriate inputs are re-
ceived. IOCHRDY is asynchronously driven LOW if the
PCnet-ISA
synchronously when the PCnet-ISA
When the PCnet-ISA
all the signals it generates are synchronous to the on-
chip 20 MHz clock.
DMA Transfers
The BIU will initiate DMA transfers according to the type
of operation being performed. There are three primary
types of DMA transfers:
1. Initialization Block DMA Transfers
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controller needs a wait state. It is released
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controller has support for the 4-byte
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controller is the Current Master,
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controller to the system
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controller is ready.
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controller is
controller is
AMD
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