am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 60

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

On receipt of the first packet with valid ETD following re-
set or link fail, the T-MAU will use the inferred polarity
information to configure its RXD input, regardless of its
previous state. On receipt of a second packet with a
valid ETD with correct polarity, the detection/correction
algorithm will “lock-in” the received polarity. If the sec-
ond (or subsequent) packet is not detected as
confirming the previous polarity decision, the most re-
cently detected ETD polarity will be used as the default.
Note that packets with invalid ETD have no effect on up-
dating the previous polarity decision. Once two
consecutive packets with valid ETD have been re-
ceived, the T-MAU will lock the correction algorithm until
either a Link Fail condition occurs or RESET is asserted.
During polarity reversal, an internal POL signal will be
active. During normal polarity conditions, this internal
POL signal is inactive. The state of this signal can be
read by software and/or displayed by LED when en-
abled by the LED control bits in the ISA Bus
Configuration Registers (ISACSR5, 6, 7).
Twisted Pair Interface Status
Three internal signals (XMT, RCV and COL) indicate
whether the T-MAU is transmitting, receiving, or in a col-
lision state. These signals are internal signals and the
behavior of the LED outputs depends on how the LED
output circuitry is programmed.
The T-MAU will power up in the Link Fail state and the
normal algorithm will apply to allow it to enter the Link
Pass state. In the Link Pass state, transmit or receive
activity will be indicated by assertion of RCV signal go-
ing active. If T-MAU is selected using the PORTSEL bits
in CSR15, when moving from AUI to T-MAU selection,
the T-MAU will be forced into the Link Fail state.
In the Link Fail state, XMT, RCV and COL are inactive.
Collision Detect Function
Activity on both twisted pair signals RXD and TXD
constitutes a collision, thereby causing the COL signal
to be asserted. (COL is used by the LED control circuits)
COL will remain asserted until one of the two colliding
signals changes from active to idle. COL stays active for
2 bit times at the end of a collision.
Signal Quality Error (SQE) Test
(Heartbeat) Function
The SQE function is disabled when the 10BASE-T port
is selected and in Link Fail state.
Jabber Function
The Jabber function inhibits the twisted pair transmit
function of the T-MAU if theTXD circuit is active for an
excessive period (20 ms–150 ms). This prevents any
one node from disrupting the network due to a ‘stuck-on’
or faulty transmitter. If this maximum transmit time is ex-
ceeded, the T-MAU transmitter circuitry is disabled, the
JAB bit is set (CSR4, bit 1), and the COL signal as-
serted. Once the transmit data stream to the T-MAU is
removed, an “unjab” time of 250 ms– 750 ms will elapse
1-534
AMD
P R E L I M I N A R Y
Am79C961
before the T-MAU deasserts COL and re-enables the
transmit circuitry.
Power Down
The T-MAU circuitry can be made to go into low power
mode. This feature is useful in battery powered or low
duty cycle systems. The T-MAU will go into power down
mode when RESET is active, coma mode is active, or
the T-MAU is not selected. Refer to the Power Down
Mode section for a description of the various power
down modes.
nal logic of the T-MAU and places the device into power
down mode. In this mode, the Twisted Pair driver pins
(TXD ,TXP ) are asserted LOW, and the internal T-
MAU status signals (LNKST, RCVPOL, XMT, RCV and
COLLISION) are inactive.
Once the SLEEP pin is deasserted, the T-MAU will be
forced into the Link Fail state. The T-MAU will move to
the Link Pass state only after 5–6 link beat pulses and/or
a single received message is detected on the RXD
pair.
In Snooze mode, the T-MAU receive circuitry will re-
main enabled even while the SLEEP pin is driven LOW.
The T-MAU circuitry will always go into power down
mode if RESET is asserted, coma is enabled, or the T-
MAU is not selected.
EADI (EXTERNAL ADDRESS DETECTION
INTERFACE)
This interface is provided to allow external address filter-
ing. It is selected by setting the EADISEL bit in
ISACSR2. This feature is typically utilized for terminal
servers, bridges and/or router type products. The use of
external logic is required to capture the serial bit stream
from the PCnet-ISA
of stored addresses or identifiers, and perform the de-
sired function.
The EADI interface operates directly from the NRZ de-
coded data and clock recovered by the Manchester
decoder or input to the GPSI, allowing the external ad-
dress detection to be performed in parallel with frame
reception and address comparison in the MAC Station
Address Detection (SAD) block.
SRDCLK is provided to allow clocking of the receive bit
stream into the external address detection logic.
SRDCLK runs only during frame reception activity.
Once a received frame commences and data and clock
are available, the EADI logic will monitor the alternating
(“1,0”) preamble pattern until the two ones of the Start
Frame Delimiter (“1,0,1,0,1,0,1,1”) are detected, at
which point the SF/BD output will be driven HIGH.
After SF/BD is asserted the serial data from SRD should
be de-serialized and sent to a content addressable
memory (CAM) or other address detection device.
Any of the three conditions listed above resets the inter-
+
controller, compare it with a table