am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 56

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

required, the MORE bit will be set. If all 16 attempts ex-
perienced collisions, the RTRY bit (in TMD2) will be set
(ONE and MORE will be clear), and the transmit mes-
sage will be flushed from the FIFO. If retries have been
disabled by setting the DRTY bit in the MODE register
(CSR15), the MAC Engine will abandon transmission of
the frame on detection of the first collision. In this case,
only the RTRY bit will be set and the transmit message
will be flushed from the FIFO.
If a collision is detected after 512 bit times have been
transmitted, the collision is termed a late collision. The
MAC Engine will abort the transmission, append the jam
sequence, and set the LCOL bit. No retry attempt will be
scheduled on detection of a late collision, and the FIFO
will be flushed.
The IEEE 802.3 Standard requires use of a “truncated
binary exponential backoff” algorithm which provides a
controlled pseudo-random mechanism to enforce the
collision backoff interval, before re-transmission is
attempted.
The PCnet-ISA
rithm, which suspends the counting of the slot time/IPG
during the time that receive carrier sense is detected.
This algorithm aids in networks where large numbers of
nodes are present, and numerous nodes can be in
collision. The algorithm effectively accelerates the
increase in the backoff time in busy networks, and al-
lows nodes not involved in the collision to access the
channel while the colliding nodes await a reduction in
channel activity. Once channel activity is reduced, the
nodes resolving the collision time out their slot time
counters as normal.
Manchester Encoder/Decoder
(MENDEC)
The integrated Manchester Encoder/Decoder provides
the PLS (Physical Layer Signaling) functions required
for a fully compliant IEEE 802.3 station. The MENDEC
provides the encoding function for data to be transmitted
on the network using the high accuracy on-board oscil-
lator, driven by either the crystal oscillator or an external
CMOS-level compatible clock. The MENDEC also pro-
vides the decoding function from data received from the
network. The MENDEC contains a Power On Reset
(POR) circuit, which ensures that all analog portions of
the PCnet-ISA
state during power-up, and prevents erroneous data
transmission and/or reception during this time.
1-530
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:
“At the end of enforcing a collision (jamming),
the CSMA/CD sublayer delays before attempt-
ing to re-transmit the frame. The delay is an
integer multiple of slotTime. The number of slot
times to delay before the nth re-transmission at-
tempt is chosen as a uniformly distributed
random integer r in the range:
0
AMD
r < 2
k
, where k = min (n,10).”
+
+
controller are forced into their correct
controller provides an alternative algo-
P R E L I M I N A R Y
Am79C961
External Crystal Characteristics
When using a crystal to drive the oscillator, the crystal
specification shown in the specification table may be
used to ensure less than 0.5 ns jitter at DO .
* Requires trimming crystal spec; no trim is 50 ppm total
External Clock Drive Characteristics
When driving the oscillator from an external clock
source, XTAL2 must be left floating (unconnected). An
external clock having the following characteristics must
be used to ensure less than 0.5 ns jitter at DO .
MENDEC Transmit Path
The transmit section encodes separate clock and NRZ
data input signals into a standard Manchester encoded
serial bit stream. The transmit outputs (DO ) are de-
signed to operate into terminated transmission lines.
When operating into a 78
line, the transmit signaling meets the required output
levels and skew for Cheapernet, Ethernet, and
IEEE-802.3.
Transmitter Timing and Operation
A 20 MHz fundamental-mode crystal oscillator provides
the basic timing reference for the MENDEC portion of
the PCnet-ISA
two to create the internal transmit clock reference. Both
clocks are fed into the Manchester Encoder to generate
the transitions in the encoded data stream. The internal
transmit clock is used by the MENDEC to internally syn-
chronize the Internal Transmit Data (ITXDAT) from the
Clock Frequency:
Rise/Fall Time (tR/tF):
XTAL1 HIGH/LOW Time
XTAL1 Falling Edge to
Falling Edge Jitter:
Parameter
1.Parallel Resonant
2.Resonant Frequency Error
3.Change in Resonant Frequency
4.Crystal Capacitance
5.Motional Crystal
6.Series Resistance
7.Shunt Capacitance
8.Drive Level
(tHIGH/tLOW):
Frequency
(CL = 20 pF)
With Respect To Temperature
Capacitance (C1)
(0 – 70 C; CL = 20 pF)*
External Crystal Characteristics
+
controller. The crystal input is divided by
Min
–50
–40
terminated transmission
20 MHz 0.01%
< 6 ns from 0.5 V
to V
40 – 60%
duty cycle
< 0.2 ns at
2.5 V input (V
DD
0.022
Nom
20
–0.5
TBD
Max
+50
+40
20
25
7
DD
/2)
PPM
PPM
MHz
mW
Unit
pF
pF
pF