am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 65

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

All accesses to 8-bit resources (which do not return
MEMCS16 or IOCS16) use SD0-7. If an odd byte is ac-
cessed, the Current Master swap buffer turns on. During
an odd byte read the swap buffer copies the data from
SD0-7 to the high byte. During an odd byte write the Cur-
rent Master swap buffer copies the data from the high
byte to SD0-7. The PCnet-ISA
ured to be an 8-bit I/O resource even in a 16-bit system;
this is set by the EEPROM. It is recommended that the
PCnet-ISA
bus cycles for maximum compatibility with PC/AT clone
motherboards.
When the PCnet-ISA
such as a PC/XT, SBHE and IOCS16 must be left un-
connected (these signals do not exist in the PC/XT).
This will force ALL resources (I/O and memory) to sup-
port only 8-bit bus cycles. The PCnet-ISA
function in an 8-bit system only if configured for Shared
Memory Mode.
Accesses to 16-bit resources (which do return
MEMCS16 or IOCS16) use either or both SD0–7 and
SD8–15. A word access is indicated by A0=0 and
SBHE=0 and data is transferred on all 16 data lines. An
even byte access is indicated by A0=0 and SBHE=1 and
data is transferred on SD0–7. An odd-byte access is in-
dicated by A0=1 and SBHE=0 and data is transferred on
Refresh Cycles
Although the PCnet-ISA
tor or a receiver of refresh cycles, it does need to avoid
unintentional activity during a refresh cycle in bus mas-
ter mode. A refresh cycle is performed as follows: First,
the REF signal goes active. Then a valid refresh ad-
dress is placed on the address bus. MEMR goes active,
the refresh is performed, and MEMR goes inactive. The
refresh address is held for a short time and then goes
invalid. Finally, REF goes inactive. During a refresh cy-
cle, as indicated by REF being active, the PCnet-ISA
controller ignores DACK if it goes active until it goes in-
active. It is necessary to ignore DACK during a refresh
*Motherboard SWAP logic drives
R/W
WR
WR
WR
WR
WR
RD
RD
RD
RD
RD
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controller be configured for 8-bit only I/O
A0
0
1
0
1
0
0
1
0
1
0
+
controller is in an 8-bit system
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controller is neither an origina-
SBHE
1
0
0
0
0
1
0
0
0
0
+
controller can be config-
+
controller will
CS16
1
1
0
0
1
1
0
0
x
x
P R E L I M I N A R Y
ISA Bus Accesses
Am79C961
+
Master
Master
Master
Float*
Slave
Slave
Slave
Slave
D0–7
Float
Float
SD8-15. It is illegal to have A0=1 and SBHE=1 in any
bus cycle. The PCnet-ISA+ controller returns only
IOCS16; MEMCS16 must be generated by external
hardware if desired. The use of MEMCS16 applies only
to Shared Memory Mode.
The following table describes all possible types of ISA
bus accesses, including Permanent Master as Current
Master and PCnet-ISA
The PCnet-ISA
ory while it is Current Master. Any descriptions of 8-bit
memory accesses are for when the Permanent Master
is Current Master.
The two byte columns (D0–7 and D8–15) indicate
whether the bus master or slave is driving the byte.
CS16 is a shorthand for MEMCS16 and IOCS16.
Bus Master Mode
The PCnet-ISA
Master only in systems that support bus mastering. In
addition, the system is assumed to support 16-bit
memory (DMA) cycles (the PCnet-ISA
not use the MEMCS16 signal on the ISA bus). This does
not preclude the PCnet-ISA+ controller from doing 8-bit
I/O transfers. The PCnet-ISA
as a bus master in 8-bit platforms such as the PC/XT.
because some motherboards generate a false DACK at
that time.
Address PROM Cycles External PROM
The Address PROM is a small (16 bytes) 8-bit PROM
connected to the PCnet-ISA
Bus. The PCnet-ISA
ISA I/O bus cycles for the address PROM; this limitation
is transparent to software and does not preclude 16-bit
software I/O accesses. An access cycle begins with the
Permanent Master driving AEN LOW, driving the ad-
dresses valid, and driving IOR active. The PCnet-ISA
controller detects this combination of signals and
Master
Master
Master
Master
D8–15
Float*
Slave
Slave
Float
Float
Float
+
+
controller will not work with 8-bit mem-
controller can be configured as a Bus
+
controller will support only 8-bit
+
controller as Current Master.
Low byte RD
High byte RD with swap
16-Bit RD converted to
low byte RD
High byte RD
16-Bit RD
Low byte WR
High byte WR with swap
16-Bit WR converted to
low byte WR
High byte WR
16-Bit WR
+
+
controller will not function
controller Private Data
Comments
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controler does
AMD
1-539
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