am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 91

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

can be accessed. All registers are 16 bits. The “Default”
value is the value in the register after reset and is
hexadecimal.
Refer to the section “LEDs” for information on LED
control logic.
ISACSR0: Master Mode Read Active
Bit
3-0
15-4
ISACSR1: Master Mode Write Active
Bit
3-0
15-4
*This value can be 0000H for systems that do not support
EEPROM option.
ISACSR
0
1
2
3
4
5
6
7
8
MSWRA
MSRDA
Name
Name
RES
RES
MNEMONIC
MSRDA
MSWRA
MC
EC
LED0
LED1
LED2
LED3
SC
This register is used to tune the
MEMR command signal active
time. The value stored in MSRDA
defines the number of 50 ns peri-
ods that the command signal is
active. The default value of 5h in-
dicates 250 ns pulse widths. A
value of 0 or 1 will generate 50 ns
wide commands.
Reserved locations. Written as
zero and read as undefined.
This register is used to tune the
MEMW command signal active
time.
MSWRA defines the number of
50 ns periods that the command
signal is active. The default value
of 5h indicates 250 ns pulse
widths. A value of 0 or 1 will gen-
erate 50 ns wide commands.
Reserved locations. Written as
zero and read as undefined.
Default
0005H
0005H
0002H
8000H*
0000H
0084H
0008H
0090H
0000H
The
Description
Description
value
Master Mode
Read Active
Master Mode
Write Active
Miscellaneous
Configuration
EEPROM
Configuration
Link Integrity
Default: RCV
Default: RCVPOL
Default: XMT
Software
Configuration
(Read-Only
register)
Name
stored
P R E L I M I N A R Y
Am79C961
in
ISACSR2: Miscellaneous Configuration
Bit
15 MODE_STATUS Mode Status. This is a read-only
14 TMAU_LOOPE
13
12
11 ISA_PROTECT
10 EISA_DECODE EISA Decode. This control bit al-
9
P&P_ACT
Reserved
SLOT_ID
Name
register which indicates whether
the PCnet-ISA
shared memory mode.
condition
memory while a clear condition
indicates bus-master condition.
10BASE-T External Loop back
Enable. This bit is usable only
when 10BASE-T is selected AND
PCnet-ISA
back. External loop back is set
during initialization via the MODE
register. When TMAU_LOOPE
is set, a board level test is en-
abled via a loop back clip which
ties the 10BASE-T RJ45 transmit
pair to the receiver pair. This will
test all external components (i.e.
transformers, resistors, etc.) of
the 10BASE-T path. TMAU_
LOOPE assertion is not suitable
for live network tests.
TMAU_LOOPE is deasserted,
default condition, external loop
back in 10BASE-T is allowed.
Written with zero and read as un-
defined.
Slot Identification. This is a read-
only register bit which indicates if
PCnet-ISA
bit slot. Reading a one indicates
an 8 bit slot. Zero indicates a
16-bit slot. (SLOT_ID bit is not
valid after the INIT bit is set in
CSR0.)
ISA Protect. When set, the
ISACSR’s 0-2 and 4-7 are pro-
tected from being written over by
software drivers.
PROTECT is cleared, ISACSR’s
0-7 are allowed to be written over
by software and reset by reading
the Software reset I/O location.
(Default is zero)
lows EISA product identifier
registers 12-bit decode xC80 -
xC83 (4 Bytes). Default is zero.
Plug and Play Active. When this
bit is set, PCnet-ISA
active after serially reading the
EEPROM. If check sum failure
exist,
beome active and alternate
PCnet-ISA
Description
+
+
is either in an 16 or 8
indicates
is in external loop
+
is configured in
+
+
When ISA_
will become
AMD
will
shared-
When
1-565
A set
not