am79c961 Advanced Micro Devices, am79c961 Datasheet - Page 55

• Manufacturer Part Number: am79c961
• Description: Pcnettm-isa Jumperless Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

The IEEE 802.3 Standard also allows optional two part
deferral after a receive message.
The MAC engine implements the optional receive two
part deferral algorithm, with a first part inter-frame-spac-
ing time of 6.0
inter-frame-spacing interval is therefore 3.6 s.
The PCnet-ISA
deferral algorithm as specified in Section 4.2.8 (Process
Deference). The Inter Packet Gap (IPG) timer will start
timing the 9.6 s InterFrameSpacing after the receive
carrier is de-asserted. During the first part deferral
(InterFrameSpacingPart1 - IFS1) the PCnet-ISA
troller will defer any pending transmit frame and respond
to the receive message. The IPG counter will be reset to
zero continuously until the carrier de-asserts, at which
point the IPG counter will resume the 9.6 s count once
again. Once the IFS1 period of 6.0 s has elapsed, the
PCnet-ISA
deferral (InterFrameSpacingPart2 - IFS2) of 3.6
Once IFS1 has completed, and IFS2 has commenced,
the PCnet-ISA
packet if a transmit packet is pending. This means that
the PCnet-ISA
receive packet, since it will start to transmit, and gener-
ate a collision at 9.6 s. The PCnet-ISA+ controller will
guarantee to complete the preamble (64-bit) and jam
(32-bit) sequence before ceasing transmission and in-
voking the random backoff algorithm.
In addition, transmit two part deferral is implemented as
an option which can be disabled using the DXMT2PD bit
(CSR3). Two-part deferral after transmission is useful
for ensuring that severe IPG shrinkage cannot occur in
specific circumstances, causing a transmit message to
follow a receive message so closely as to make them
indistinguishable.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.1:
“Note : It is possible for the PLS carrier sense
indication to fail to be asserted during a collision
on the media. If the deference process simply
times the interpacket gap based on this indica-
tion it is possible for a short interFrame gap to
be generated, leading to a potential reception
failure of a subsequent frame. To enhance sys-
tem
measures, as specified in 4.2.8, are recom-
mended when InterFrameSpacingPart1 is
other than zero:
(1) Upon completing a transmission, start timing
(2) When timing an interpacket gap following re-
the interpacket gap, as soon as transmitting
and carrierSense are both false.
ception, reset the interpacket gap timing if
carrier Sense becomes true during the first 2/3
of the interpacket gap timing interval. During the
final 1/3 of the interval the timer shall not be re-
set to ensure fair access to the medium. An
initial period shorter than 2/3 of the interval is
permissible including zero.”
robustness
+
controller will begin timing the second part
+
+
controller will not attempt to receive the
+
controller will not defer to a receive
controller will perform the two-part
s. The second part of the
the
following
optional
P R E L I M I N A R Y
+
con-
Am79C961
s.
During the time period immediately after a transmission
has been completed, the external transceiver (in the
case of a standard AUI connected device), should gen-
erate the SQE Test message (a nominal 10 MHz burst of
5-15 bit times duration) on the CI pair (within 0.6 s –
1.6 s after the transmission ceases). During the time
period in which the SQE Test message is expected the
PCnet-ISA+ controller will not respond to receive carrier
sense.
The PCnet-ISA
“blinding” period within 0 - 4.0 s from de-assertion of
carrier sense after transmission. This effectively means
that when transmit two part deferral is enabled
(DXMT2PD is cleared) the IFS1 time is from 4 s to 6 s
after a transmission. However, since IPG shrinkage be-
low 4
configured network, and since the fragment size will be
larger than the 4
counter will be reset by a worst case IPG shrinkage/frag-
ment scenario and the PCnet-ISA
its transmission. In addition, the PCnet-ISA+ controller
will not restart the “blinding” period if carrier is detected
within the 4.0 s – 6.0 s IFS1 period, but will com-
mence timing of the entire IFS1 period.
Contention resolution (collision handling)
Collision detection is performed and reported to the
MAC engine by the integrated Manchester Encoder/
Decoder (MENDEC).
If a collision is detected before the complete preamble/
SFD sequence has been transmitted, the MAC Engine
will complete the preamble/SFD before appending the
jam sequence. If a collision is detected after the pream-
ble/SFD has been completed, but prior to 512 bits being
transmitted, the MAC Engine will abort the transmis-
sion, and append the jam sequence immediately. The
jam sequence is a 32-bit all zeroes pattern.
The MAC Engine will attempt to transmit a frame a total
of 16 times (initial attempt plus 15 retries) due to normal
collisions (those within the slot time). Detection of colli-
sion will cause the transmission to be re-scheduled,
dependent on the backoff time that the MAC Engine
computes. If a single retry was required, the ONE bit will
be set in the Transmit Frame Status (TMD1 in the Trans-
mit Descriptor Ring). If more than one retry was
See ANSI/IEEE Std 802.3-1990 Edition,
7.2.4.6 (1)):
“At the conclusion of the output function, the
DTE opens a time window during which it ex-
pects to see the signal_quality_erro r signal
asserted on the Control In circuit. The time win-
dow begins when the CARRIER_STATUS
becomes CARRIER_OFF. If execution of the
output function does not cause CARRIER_ON
to occur, no SQE test occurs in the DTE. The
duration of the window shall be at least 4.0 s
but no more than 8.0 s. During the time win-
dow the Carrier Sense Function is inhibited.”
s will rarely be encountered on a correctly
+
controller implements a carrier sense
s blinding window, then the IPG
+
controller will defer
AMD
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