tsc693e ETC-unknow, tsc693e Datasheet - Page 10

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

3. MEMORY CONTROLLER FUNCTIONS
All support functions of the ERC32 except for the local clock/oscillator and address and
data bus drivers (buffers and latches) are incorporated in one single chip memory
controller unit (MEC).
The MEC is designed to interface the IU and the FPU to external memory and I/O units
thus forming a system, with which computers for on-board embedded real-time
applications can be built. In order to achieve this the MEC constitutes all necessary
support and on-chip resources accordingly:
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The MEC interfaces directly to the address, data, and control buses of the IU and FPU,
requiring no additional components. It also interfaces directly to external memory and
I/O units only requiring additional buffers for the address and data bus.
The architecture of the MEC is illustrated in Figure 2.
MATRA MHS
Rev. D (10 Apr. 97)
System start up control and reset
Power down mode control
System clock
Watchdog function
Memory interface to RAM ranging from 256 Kbyte to 32 Mbyte
Memory interface to PROM ranging from 128 Kbyte to 4 Mbyte
I/O interface to exchange memory (e.g. DPRAM) ranging from 4 Kbyte to 512
Kbyte.
I/O interface to four peripherals
DMA interface
Bus arbiter
Programmable wait-state generator
Programmable memory access protection
Memory redundancy control
EDAC, with byte and halfword write support
Trap handler including 15-level interrupt controller
One 32-bit general purpose timer with 16-bit scaler
One 32-bit timer with 8-bit scaler (Real-Time-Clock)
UART function with two serial channels
Built-in concurrent error detection including support for master/slave checking of
IU and FPU
System error handler
Parity control on system bus
Test support including a minimal TAP interface
TSC693E
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