tsc693e ETC-unknow, tsc693e Datasheet - Page 26

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
The segment access protection can also be used as a block protect function by setting the
BP bit in the MEC Control Register. The BP bit inverts the address criterion for the
protection function so that any access within the segment is detected.
If a write access protection error is detected a memory exception is generated and the
SFSR and Failing Address Register is updated as for unimplemented area accesses,
see also paragraph 3.17.
In normal mode, (BP=0), a memory exception is generated only if both segments
indicated a write protection error. In block protect mode (BP=1), a memory exception is
generated if any of the segments indicate a write protection error.
3.7.3. Boot PROM Write Protection
The MEC supports PROM write only when it is qualified by the external enable signal
ROMWRT and the enable bit in the Memory Configuration Register (see page 52).
The MEC only supports byte write operations for an 8-bit wide PROM and only word
write operations for a 40-bit wide PROM.
If a write access to PROM is attempted when any of the above conditions are not
fulfilled, the SFSR and Failing Address Register is updated as for unimplemented area
accesses, see also paragraph 3.17.
3.8. Register Access Protection
All MEC registers except the UART RX and TX registers are readable in all access
modes: user, supervisor, and DMA. The UART RX and TX registers are only readable
in supervisor mode. The MEC allows word, halfword and byte accesses when a register
is read. The total 32-bit data (together with the parity bit) are thus always issued on the
data bus.
All MEC registers which are writeable, are writeable only in supervisor mode or in
DMA mode if the CPUHALT* is active and only as full 32-bit size data write accesses
to the registers.
If a register access violation is performed by the IU, the memory exception output is
asserted. If a register access violation is performed by the DMA, the memory exception
output (MEXC*) and the DMA access error interrupt output are asserted.
MATRA MHS
Rev. D (10 Apr. 97)
26