tsc693e ETC-unknow, tsc693e Datasheet - Page 25

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
3.7. Memory Access Protection
3.7.1. Unimplemented Areas
Accesses to all unimplemented memory areas are handled by the MEC and detected as
illegal, according to Table 3 (page 18). The memory and I/O configuration registers
define the size of memory and I/O areas. The unused area of the memory space,
dependent on the programming of the memory size, is decoded as illegal.
If an access from the IU is attempted to an illegal area, the memory exception output is
asserted. If an access from the DMA is attempted to an illegal area, the memory
exception output (MEXC*) and the DMA access error interrupt output are asserted.
For the extended areas no access protection is implemented. However, since these areas
are bus ready( BUSRDY*) controlled the bus timeout function will detect an access to
an unimplemented extended area.
When the IU issues the trap service routine, the contents of the MEC System Fault
Status Register (SFSR) give the cause of the exception.
When a memory data access violation error occurs (RAM write protection or illegal
area) the associated bus address is latched in a separate register, MEC Failing Address
Register (FAR). With memory data access is meant IU operand fetch or DMA. An IU
instruction fetch error will not latch the bus address.
For further actions taken see paragraph 3.17.
3.7.2. RAM Write Access Protection
In addition to the access protection defined by the fixed memory map in the MEC which
will detect any access to unimplemented and illegal addresses, the MEC can be
programmed to detect and mask write accesses in any part of the RAM. The protection
scheme is enabled only for data area, not for the instruction area.
The programmable write access protection is segment based. A segment defines an area
where write cycles are allowed. Any write cycle outside a segment is trapped and does
not change the memory contents. Two segments are implemented. Each segment is
implemented with two registers: the Segment Base Register and the Segment End
Register. The segment base register contains the start address of the segment, and
enabling bits for supervisor/user mode (SE/UE). The segment end register contains the
first address outside the segment, i.e. last address of segment plus one word. Only word
aligned addresses are supported. The segments are only active during RAM access, i.e.
they can only be mapped to the RAM area.
If both the SE and UE bits of the Segment Base Register are cleared, write protection is
effectively disabled for that segment.
MATRA MHS
Rev. D (10 Apr. 97)
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