tsc693e ETC-unknow, tsc693e Datasheet - Page 19

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

3.3. DMA Interface
The MEC supports Direct Memory Access (DMA). The DMA unit requests access to
the processor bus by asserting the DMA request signal, DMAREQ*. When the DMA
unit receives the DMAGNT* signal in response, the processor bus is granted. In case the
processor is in the power down mode the IU is permanent three-stated, and a
DMAREQ* will directly give a DMAGNT*. The detailed timing for DMA accesses is
defined in Appendix A.
It is possible to enable/disable DMA access to the system bus by programming the
MEC Control Register (see page 51). The default status after system reset is DMA
enabled (i.e. permitted).
If DMA is enabled, the MEC asserts BHOLD* and deasserts AOE*, COE*, and DOE*
following an DMA Request and then asserts DMA Grant.
A memory cycle started by the processor is not interrupted by a DMA access before it is
finished. The following signals shall be used by the DMA unit during the access:
If no subsequent DMA cycles are to be issued the DMA unit shall remove the
DMAREQ* signal as soon as it has fetched the data on read after that it has received
MATRA MHS
Rev. D (10 Apr. 97)
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DMAREQ* to be generated by the DMA unit asking for access
DMAGNT* generated by the MEC when DMA access is granted
SYSCLK from the MEC to be used as synchronizing clock
A[31:0], ASI[3:0] address and SIZE[1:0], WRT, WE*, RD, DXFER,
LDSTO, LOCK to be generated by the DMA unit.
SIZE0 and SIZE1, to be driven by the DMA during DMA transfers. Note
that only word transfers are allowed in DMA mode, which means that the
values of the size bits must always be driven to SIZE0 = 0 and SIZE1 = 1
in DMA mode.
APAR, ASPAR and IMPAR parity bits, to be generated by the DMA unit
in case parity is enabled for the DMA
D[31:0] data generated by the DMA unit in case of write cycle or fetched
by the DMA unit during read cycle
DPARIO, data parity, to be generated and possibly checked by the DMA
unit in case parity is enabled for the DMA
DMAAS line used for address strobe to be generated by the DMA unit
when the address is valid. Assertion of this signal will initiate the memory
access.
DRDY* line used for indicating data ready for the DMA unit or data
written on write. It is generated by the MEC
MEXC* generated by the MEC indicating a memory access exception
when no valid data can be supplied from the memory system, e.g. access
violation or error.
TSC693E
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