tsc693e ETC-unknow, tsc693e Datasheet - Page 46

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tsc693e

Manufacturer Part Number
tsc693e
Description
Memory Controller
Manufacturer
ETC-unknow
Datasheet
The following tables show when updating of the registers is made.
U : register updated, parity updated
SFSR : System Fault Status register
ERSR : Error and Reset Status Register
FAR : Failing Address Register
* SFSR is updated at the time of Watchdog interrupt while ERSR is only updated if the
Watchdog elapsed causes a halt or reset.
MATRA MHS
Rev. D (10 Apr. 97)
Asynchronous trap events
Watchdog timeout *
Ext. interrupt 4
Real time clock interrupt
General purpose timer interrupt
Ext. interrupt 3
Ext. interrupt 2
DMA session timeout
DMA access error
UART error interrupt
EDAC correctable error
UART B data received or transmitter
ready interrupt
UART A data received or
transmitter ready interrupt
Ext. interrupt 1
Ext. interrupt 0
Masked hardware error interrupt
Synchronous trap events
Control bus parity error
Address bus parity error
Data bus parity error
Memory access protection
error
Unimplemented address
violation
MEC register violation error
EDAC uncorrectable error
Bus time-out
System bus error
SFSR
U
U
U
U
U
U
U
U
U
SFSR
U
U
U
U
U
FAR
U
U
U
U
U
U
U
U
U
ERSR
U
U
FAR
U
U
TSC693E
46

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