tsc693e ETC-unknow, tsc693e Datasheet - Page 12

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
3.1. Data Types
Data type definitions follow the SPARC standard version 7. A byte is 8 bits wide, a
halfword is 16 bits wide, a word is 32 bits wide, and a double word is 64 bits wide.
Organization and addressing of data in memory follow the "Big-Endian" convention
wherein lower addresses contain the high-order bytes. For a stored word, address N
corresponds to the most significant byte and N+3 corresponds to the least significant
byte.
3.2. Memory Interface
3.2.1. Memory Control Signals
The MEC asserts a system address latch enable signal, ALE*, when the IU address or
the DMA address is valid. This signal is asserted once in every memory access cycle.
Four buffer enable signals are provided, RAMBEN*, ROMBEN*, MEMBEN* and
IOBEN*. RAMBEN* is asserted during RAM access. ROMBEN* is asserted during
boot PROM access. MEMBEN* is asserted both during RAM and boot PROM access.
IOBEN* is asserted during I/O, Extended general area and exchange memory access.
DDIR and DDIR* are output by the MEC to indicate buffer direction.
As RAM chip select signals MEMCS*(9:0) are provided. The boot PROM chip select
signal is ROMCS*. Four I/O device chip select signals are provided, IOSEL(3:0).
EXMCS* is used as chip select signal for exchange memory.
For RAM and boot PROM write access two strobe pairs are provided, MEMWR1*(1:0)
and MEMWR2*(1:0). MEMWR1* is used to strobe data, D(31:0) into memory.
MEMWR2* is used to strobe check bits, CB(6:0) and parity, DPARIO, into memory.
For I/O and exchange memory write access the IOWR* strobe is provided.
As output enable to memory during read access, OE*(1:0) is provided.
BUSRDY* is used to control access cycle length when accessing I/O, exchange memory
and extended areas.
BUSERR* is used to signal erroneous access to the MEC when accessing I/O, exchange
memory and extended areas.
3.2.2. RAM
The MEC is reprogrammable to interface with a number of different RAM sizes and
organisations. The table below shows all possible memory sizes and organisations:
MATRA MHS
Rev. D (10 Apr. 97)
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