tsc693e ETC-unknow, tsc693e Datasheet - Page 69

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
WRT - Advanced Write (input)
WRT is an early write signal, asserted by the processor during the first store address
cycle of integer single or double store instructions, the first store address cycle of
floating-point single or double store instructions, and the second load-store address
cycle of atomic load-store instructions. WRT is sent out unlatched and is latched in the
MEC before it is used. A DMA unit must supply this signal during a DMA session,
deasserted low for read and asserted high for write accesses.
IMPAR - IU to MEC Control Parity (input)
This input is used by the MEC to check the odd parity over the LDSTO, DXFER,
LOCK, WRT, RD, and WE* signals. This signal must be driven by the DMA if DMA
uses parity.
AOE* - Address Output Enable (output)
The MEC deasserts this signal when an external master (DMA unit) uses the address
bus.
COE* - Control Output Enable (output)
The MEC deasserts this signal when an external master (DMA unit) uses the control
bus.
DOE* - Data Output Enable (output)
The MEC deasserts this signal when an external master (DMA unit) uses the data bus.
BHOLD* - Bus Hold (output)
The MEC asserts this signal during DMA accesses.
MDS* - Memory Data Strobe (output)
During nominal execution with the IU as bus master, MDS* is asserted by the MEC to
enable the clock to the instruction register of the IU (during an instruction fetch) or to
the load result register (during a data fetch) while the pipeline is frozen with an
MHOLDA/B*.
MATRA MHS
Rev. D (10 Apr. 97)
69