tsc693e ETC-unknow, tsc693e Datasheet - Page 70

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
MEXC* - Memory Exception (output)
Assertion of this signal by the MEC initiates an instruction access exception or data
access exception trap and indicates to the IU that the memory system was unable to
supply a valid instruction or data. It is asserted when a parity error, uncorrectable EDAC
error, access violation, bus time-out or system bus error is detected. If this signal is
asserted during a DMA transfer, the DMA must withdraw its DMA request and end the
DMA cycle.
MHOLD* - Memory Bus Hold (output)
MHOLD* is used to freeze the clock to both the IU and floating-point unit during a
cache miss (for systems with cache memory) or when accessing a slow memory. It is
generated by the MEC to insert wait states during memory or I/O accesses.
MATRA MHS
Rev. D (10 Apr. 97)
70