tsc693e ETC-unknow, tsc693e Datasheet - Page 74

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
IOBEN* - IO Buffer Enable (output)
IOBEN* is asserted during I/O access, extended I/O area extended general area and
exchange memory access in order to enable the data buffers for the I/O and exchange
memory.
EXMCS* - Exchange Memory Chip Select (output)
EXMCS* is asserted when the exchange memory is accessed.
BUSRDY* - Bus Ready (input)
BUSRDY* is to be generated by a unit in the I/O area, exchange memory area or in the
extended areas, which requires extended time when accessed in addition to the
preprogrammed number of wait states. (Note however that waitstates can not be
preprogrammed for units in the extended general area, only for extended I/O, boot
PROM and RAM)
BUSERR* - Bus Error (input)
BUSERR* is to be generated together with BUSRDY* by a unit in the I/O area,
exchange memory area or in the extended areas if an error is detected by the accessed
unit during an access.
DMAREQ* - DMA Request (input)
DMAREQ* is to be issued by a unit requesting the access to the processor bus as a
master.
DMAGNT* - DMA Grant (output)
DMAGNT* is generated by the MEC as a response to a DMAREQ*. DMAGNT* is
sent after that the MEC has asserted BHOLD* and deasserted AOE*, DOE*, and COE*
for holding and three-stating the IU.
MATRA MHS
Rev. D (10 Apr. 97)
74