tsc693e ETC-unknow, tsc693e Datasheet - Page 84

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

MATRA MHS
Rev. D (10 Apr. 97)
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Diagram Name
CLK2 to SYSCLK Skew
RAM Load-Store sequence at 0 WS with EDAC and/or Parity Protection
RAM Load at 1 waitstate with EDAC and/or Parity Protection
RAM Store at 1 waitstate with EDAC and/or Parity Protection
RAM Load with Correctable Error
RAM Load with Uncorrectable Error
RAM Load at 1 Waitstate with Access Violation
RAM Store at 1 Waitstate with Access Violation
RAM Store at 0 Waitstate with Access Violation
RAM Store Byte/Halfword with No Error / Correctable Error
RAM Store Byte/Halfword with Uncorrectable Error
RAM Store Double
RAM Store Double with exception in 2:nd word
PROM bytewide Load at 2 waitstates
PROM bytewide Store at 1 waitstate
PROM 40-bit wide Load at 2 waitstate
PROM 40-bit wide Store at 1 waitstate
MEC Register Load
MEC Register Store
Exchange Memory Load with no parity or EDAC protection
Exchange Memory Store with EDAC and/or parity protection
Exchange Memory Load with Busy and with EDAC and/or parity protection
Exchange Memory Store with Busy and with EDAC and/or parity protection
IO Load at 3 waitstates
IO Store at 2 waitstates
IO Load with Busy
IO Store at 0 waitstate with Busy
Extended Area Load with Busy
Extended Area Store with Busy
DMA RAM Load
DMA RAM Store
DMA IO Load
DMA IO Store
DMA IO Load with Exception
DMA RAM Load with Correctable Error
DMA RAM Load with Uncorrectable Error
Power Down Mode after writing to Power Down Register
TAP Control Timing
Reset Timing
Halt Timing
External Error with Reset Timing
External Error with CPUHALT Timing
Internal MEC Error with Reset Timing
Internal MEC Error with CPUHALT Timing
Edge Triggered Interrupt Timing
Level Triggered Interrupt Timing
TSC693E
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