tsc693e ETC-unknow, tsc693e Datasheet - Page 24

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

It is possible to program the number of wait states for the following combinations:
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The MEC supports wait state generation by asserting the MHOLD* output in the second
memory access cycle.
On exchange memory accesses the MEC will sense the bus ready signal (BUSRDY*)
after the first two cycles of the access. If the bus ready signal is asserted at this time the
MEC will continue with the programmed no. of wait states. However, if the bus ready
signal is deasserted, the start of the access is put on hold. Once the bus ready signal is
asserted again, the access will start with the programmed no. of waitstates.
On I/O and extended area accesses the MEC will sense the bus ready signal
(BUSRDY*) after the first cycle of the access. If the bus ready signal is asserted at this
time the MEC will continue with the programmed no. of wait states. If the bus ready
signal is deasserted at this time, the MEC will introduce wait states until the bus ready
signal is again asserted.
Note the difference between wait state handling for exchange memory and wait state
handling for I/O. For exchange memory, the access will start when BUSRDY* is
asserted, i.e. after BUSRDY* is asserted an access with the programmed no. of wait
states will be performed. BUSRDY* is then handled as for the I/O and extended area.
On the other hand, during I/O and extended area access, assertion of BUSRDY* signals
the end of the access, i.e. the access will finish one cycle after BUSRDY* has been
asserted (at the earliest after the programmed no. of wait states).
A bus timeout function of 256 or 1024 system clock cycles is provided for the bus ready
controlled memory areas, 256 system clocks in the Extended RAM, Extended General
and Extended I/O areas and 1024 system clocks in the Extended PROM area. The MEC
Control Register (see page 51) is used to select this function. The default after system
reset is that the bus timeout function is enabled.
The bus timeout counter will start when the access is initiated. If the bus ready signal is
not asserted before a valid number of system clock cycles, a memory exception will
occur. For further actions taken see paragraph 3.17.
MATRA MHS
Rev. D (10 Apr. 97)
RAM read
RAM write
PROM read
PROM write (i.e. EEPROM write)
ExM read/write (i.e. Exchange memory read/write)
Four individual I/O peripherals read/write
TSC693E
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