tsc693e ETC-unknow, tsc693e Datasheet - Page 65

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

4.2. MEC Detailed Signal Descriptions
4.2.1. IU/FPU Interface Signals
A[31:0] - Address Bus (input)
The address bus for the MEC is an input-only bus. The MEC uses the address bus to
perform decoding, to generate select signals, and to check against the memory access
protection scheme. It is also used to address the MEC registers. In case of Direct
Memory Access, DMA, the address bus is driven by the DMA unit.
APAR - Address Bus Parity (input)
This input is used by the MEC to check the odd parity over the 32-bit address bus. In
case of Direct Memory Access, DMA, this signal must be driven by the DMA unit in
case DMA parity is enabled.
MATRA MHS
Rev. D (10 Apr. 97)
ROMWRT*
CPUHALT*
Test Access Port Signals
TCK
TRST*
TMS
TDI
TDO
UART Interface
WDCLK
RXA
RXB
TXA
TXB
Power and Clock Signals
CLK2
SYSCLK[1:0]
VCCI
VCCO
VSSI
VSSO
Number of pins
1
1
1
1
1
1
1
1
1
1
1
1
1
2
5
17
5
17
218
I
O
I
I
I
I
O
I
I
I
O
O
I
O
I
I
I
I
ROM Write Enable
Processor (IU and FPU) Halt
Test Clock
Test Reset
Test Mode Select
Test Data Input
Test Data Output
Watch Dog Clock
Receive Data channel
Receive Data channel B
Transmit Data channel A
Transmit Data channel B
Double Frequency Clock
System Clock
Main internal VCC
Output driver VCC
Main internal VSS
Output driver VSS
TSC693E
TTL
CMOS
TTL
TTL
TTL
TTL
CMOS
TTL
TTL
TTL
CMOS
CMOS
TTL
TTL/CMOS
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