tsc693e ETC-unknow, tsc693e Datasheet - Page 77

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
SYSAV - System Availability (output)
This signal is asserted whenever the system is available, i.e. when the SYSAV bit in the
ERSR is set and the CPUHALT* and SYSERR* signals are deasserted. The SYSAV bit
is cleared by reset and is programmable by software.
SYSHALT* - System Halt (input)
SYSHALT* is used by the system outside to halt the ERC32. By asserting this signal,
the MEC will assert CPUHALT* halting the IU and the FPU. This signal could be used
for testing through the DMA or the TAP interface.
NOPAR* - No Parity (input)
Assertion of this signal will disable the parity checking of all signals related to the
ERC32 local buses. The parity generation on the data bus (towards memory and IO
units) is not affected by this signal, but note that parity checking is disabled if NOPAR*
is asserted. This is a static signal and shall not change when running.
ROMWRT* - ROM Write Enable (input)
Assertion of this signal will validate (allow) programming (write operations) of the boot
PROM when EEPROM devices are used.
CPUHALT* - Processor (IU and FPU) Halt (output)
This output is intended to be connected to the HALT* inputs of the IU and of the FPU
and is used to halt the IU, the FPU and possibly other units in the system.
4.2.4. Test Access Port Signals
The following Test Access Port interface (IEEE standard 1149.1) is used to perform
boundary scan for test and debugging purposes.
TCK - Test Clock (input)
Test clock for scan registers.
MATRA MHS
Rev. D (10 Apr. 97)
77