tsc693e ETC-unknow, tsc693e Datasheet - Page 8

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

2. GENERAL OVERVIEW OF ERC32
2.1. ERC32 Overview
The objective of the ERC32 is to provide a high performance 32-bit computing core for
on-board embedded real-time computers. The core is characterized by low circuit
complexity and power consumption. Extensive concurrent error detection and support
for fault-tolerance and reconfiguration is emphasized.
In addition to the main objective, the ERC32 core is possible to use for performance
demanding research applications in deep space probes. In addition to the above
characteristics the radiation tolerance and error masking are important. By including
support for reconfigurable of the error handling the different demands from the
applications can be optimized for the best purpose in each case.
The ERC32 is to be used as a building block only requiring memory and application
specific peripherals to be added to form a complete on-board computer. All other system
support functions are provided by the core.
The ERC32 incorporates the followings functions:
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Figure 1 schematically shows a basic ERC32 computer with external functions added to
form a complete system.
MATRA MHS
Rev. D (10 Apr. 97)
Processor, which consists of one Integer Unit: TSC691E (called IU in this
document) and one Floating Point Unit: TSC692E (called FPU in this document).
The processor includes concurrent error detection facilities.
Memory Controller: TSC693E (called MEC in this document), which is a unit
consisting of all necessary support functions such as memory control and
protection, EDAC, wait state generator, timers, interrupt handler, watch dog,
UARTs, and test support. The unit also includes concurrent error detection
facilities.
One or two oscillator(s).
Buffers necessary to interface with memory and peripherals.
TSC693E
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