tsc693e ETC-unknow, tsc693e Datasheet - Page 27

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
3.9. EDAC
The MEC includes a 32-bit EDAC (Error Detection And Correction). Seven bits
(CB[6:0]) are used as check bits over the data bus. The Data Bus Parity Input/Output
signal (DPARIO) is used to check and generate the odd parity over the 32-bit data bus.
This means that altogether 40 bits are used when the EDAC is enabled.
The MEC EDAC uses a seven bit Hamming code which detects any double bit error on
the 40-bit bus as a non-correctable error. In addition, the EDAC detects all bits stuck-at-
1
one and stuck-at-zero failure for any nibble
in the data word as a non-correctable error.
Stuck-at-one and stuck-at-zero for all 32 bits of the data word is also detected as a non-
correctable error.
The EDAC corrects any single bit data error on the 40-bit bus. However, in order to
correct any error in memory (e.g. Single Event Upset induced) the data has to be read
and re-written by software as the MEC does not automatically write back the corrected
data.
1
A nibble is defined as a bit group of four within the data word, D(3:0), D(7:4) etc.
MATRA MHS
Rev. D (10 Apr. 97)
27