tsc693e ETC-unknow, tsc693e Datasheet - Page 35

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

simultaneously, the interrupt with the highest priority level is issued to the IU. If a
higher level interrupt is recognized by the MEC before the lower level interrupt request
is acknowledged, the higher level interrupt will replace the lower level interrupt request.
By programming the Interrupt Shape Register (see page 56), it is possible to define
the external interrupts to be either active low or active high and to define the external
interrupts to be either edge or level sensitive. Also, by programming the ISR, it is
possible to make one of the external interrupts generate a pulse on the EXTINTACK
output when the IU acknowledges the interrupt.
The external interrupt inputs are filtered such that both level and edge sensitive
interrupts are detected only if the external interrupt is active for at least two system
clock cycles.
Edge sensitive interrupts will be detected only when a transition occurs (from high to
low if programmed to be active low and vice-versa), i.e. the corresponding bit in IPR
will be set.
Level sensitive interrupts will be detected, i.e. the corresponding bit in IPR will be set as
long as the interrupt line is asserted. When the interrupt line is deasserted, the
corresponding bit in IPR will be cleared.
MATRA MHS
Rev. D (10 Apr. 97)
Trap
Watch Dog time-out
Ext. Interrupt 4
Real Time Clock
General purpose timer
Ext. Interrupt 3
Ext. Interrupt 2
DMA time-out
DMA access error
UART error
Correctable error in mem.
UART B Data Ready or
Transmitter Ready
UART A Data Ready or
Transmitter Ready
Ext. Interrupt 1
Ext. Interrupt 0
Masked Hardware errors
Table 5 - Interrupt Trap Type and default priority assignments
Priority
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Trap Type
0x1F
0x1E
0x1D
0x1C
0x1B
0x1A
0x19
0x18
0x17
0x16
0x15
0x14
0x13
0x12
0x11
Interrupt level/no
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TSC693E
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