tsc693e ETC-unknow, tsc693e Datasheet - Page 41

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
There is another interrupt to indicate errors, but this interrupt is common for both UART
channels.
The UART uses an internal clock which is 16 times faster than the baud-rate, and
samples each bit 16 times, to ensure error free reception. The clock is derived either
from the system clock or can use the watchdog clock with a UART oscillator input.
The baudrate of the UARTs can be programmed in the Scaler field and UBR bit of the
MEC Control Register. The scaler shall be set to:
Clock
Scaler =
- 1
32 * Baudrate * (2 - UBR)
Where Clock is either the frequency of the system clock (SYSCLK) or the watchdog
clock (WDCLK) selected by UCS (bit 23 in MEC Control Register). UBR is the value
of the UBR bit. Baudrate is the desired baudrate. Note that the resulting actual baudrate
will probably not be exactly the desired one. This is due to the fact that Scaler is an
integer number, and the above given equation may yield a non-integer result, depending
on the Clock frequency.
The UART is temporary halted when CPUHALT* is active and no transmission is
performed by the UART.
The external UART interfaces consist of one transmit data output for each UART
channel (TXA and TXB) and one receive data input for each UART channel (RXA and
RXB).
Note that no hardware handshake signals, such as CTS or RTS are implemented. Any
handshaking must be implemented in software (e.g. using XON/XOFF).
3.16. Parity Checking
The MEC includes parity checking and generation if required on the external data bus
(DPARIO). It includes parity checking on the external address bus (APAR). It also
includes parity checking on ASI and SIZE (ASPAR) together with parity generation and
checking on all internal registers. The MEC also includes parity generation and
checking on the external control bus to the IU (IMPAR). If a parity error is detected on
the external data bus, the external address, the external ASI and SIZE, the external
control bus, the memory exception output (MEXC*) is asserted. If a memory exception
event occurs the System Fault Status Register (see page 60) is updated and reflects the
type and location of parity errors.
All external parity checking can be disabled using the NOPAR* signal.
MATRA MHS
Rev. D (10 Apr. 97)
41