tsc693e ETC-unknow, tsc693e Datasheet - Page 68

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
LDSTO - Atomic Load-Store (input)
This signal is used to identify an atomic load-store to the system and is asserted by the
integer unit during all the data cycles (the load cycle and both store cycles) of atomic
load-store instructions. LDSTO is sent out unlatched and is latched in the MEC before it
is used. A DMA unit must supply this signal during a DMA session.
LOCK -Bus Lock (input)
LOCK is asserted by the processor when it needs to retain control of the bus (address
and data) for multiple cycle transactions (Load Double, Store Single and Double,
Atomic Load-Store). The bus will not be granted to another bus master as long as
LOCK is asserted. Note that BHOLD* should not be asserted in the processor clock
cycle which follows a cycle in which LOCK is asserted. LOCK is sent out unlatched and
must be latched externally before it is used. A DMA unit must supply this signal during
a DMA session.
RD - Read Access (input)
RD is used in conjunction with SIZE[1:0], ASI[3:0] and LDSTO to determine the type
of transfer and to check the write access rights of bus transactions. It may also be used to
turn off the output drivers of data RAMs during a store operation. A DMA unit must
supply this signal during a DMA session, deasserted low for write and asserted high for
read accesses.
WE* - Write Enable (input)
WE* is asserted by the integer unit during the cycle in which the store data is on the data
bus. For a store single instruction, this is during the second store address cycle; the
second and third store address cycles of store double instructions, and the third load-
store address cycle of atomic load-store instructions. It is sent out unlatched and is
latched in the MEC before it is used. To avoid writing to memory during memory
exceptions, WE* is internally qualified by MHOLD* and MEXC*. A DMA unit must
supply this signal during a DMA session, asserted low for write and deasserted high for
read accesses.
MATRA MHS
Rev. D (10 Apr. 97)
68