tsc693e ETC-unknow, tsc693e Datasheet - Page 16

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

An I/O cycle which is to be extended beyond that of the number of wait-states set in the
MEC for the corresponding I/O select output, requires that the BUSRDY* signal is
deasserted as input to the MEC. The BUSRDY* signal must be deasserted no later than
the number of system clock cycles equal to the wait-states set in the MEC after start of
the access.
The actual length of an IO cycle will equal the number of programmed waitstates,
possibly extended a number of clock cycles by deassertion of the BUSRDY* signal. If a
cycle is prolonged to more than 256 clock cycles, the Bus Timeout function will signal a
system bus error. As the BUSRDY* signal is used to extend the IO cycle, one waitstate
is minimum for I/O access. Programming the no. of IO waitstates to zero will have no
effect, i.e. one waitstate is inserted anyway.
Each I/O unit is enabled by programming the I/O Configuration Register (see page
54). The default value after system reset is no I/O unit enabled.
Each of the four I/O units is programmable to following sizes: 512 bytes, 1 Kbyte, 2
Kbytes, 4 Kbytes, 8 Kbytes, 16 Kbytes, 32 Kbytes, 64 Kbytes, 128 Kbytes, 256 Kbytes,
512 Kbytes, 1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, 16 Mbytes.
Selection of each individual I/O unit size is performed by programming the I/O
Configuration Register (see page 54). The default value after system reset is 512 bytes
for all units.
In case the I/O unit includes a parity bit, the parity will be treated in the same manner as
for the main memory. If the I/O unit does not include parity, the MEC will generate
parity to the IU. The I/O Configuration Register (see page 54) is used to determine for
each individual I/O unit if the MEC shall use parity checking and generation. The
default is no parity is implemented for the I/O units.
Since the I/O unit never includes EDAC check bits, the store subword (half-word or
byte) instruction in the I/O area is different from the store subword in the RAM area. In
the RAM area a store subword is implemented as a read-modify-write since check bits
must be generated over the whole word. In the I/O area a store subword is implemented
as a store word from a timing point of view, but the subword (byte or halfword) is
repeated by the IU on the other subwords in the full word, see Figure 4.
MATRA MHS
Rev. D (10 Apr. 97)
BUSERR*
H
H
L
L
Table 2 - Bus Transaction Response Signals
* denotes an active low signal
BUSRDY*
H
L
H
L
Action
Nothing (not ready)
Data Strobe (ready)
Nothing (not ready)
System Bus Error
TSC693E
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