tsc693e ETC-unknow, tsc693e Datasheet - Page 66

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
ASI[3:0] - Address Space Identifier (input)
These four bits constitute the Address Space Identifier (ASI), which identifies the
memory address space to which the memory access is being directed. The ASI bits are
latched by the MEC and are used to detect supervisor mode, instruction or data access,
etc. A DMA unit must supply these bits.
SIZE[1:0] - Bus Transaction Size (input)
The coding on these pins specifies for the MEC the size of the data being transferred
during a memory access. A DMA unit must drive these bits to '10', since only word
transfers are allowed in DMA mode.
ASPAR - ASI and SIZE Parity (input)
This input is used by the MEC to check the odd parity over the ASI[3:0] and the
SIZE[1:0] signals. A DMA unit must supply this bit in case DMA parity is enabled.
Note that although ASI[7:0] exist in the IU, only ASI[3:0] are connected to the MEC.
This means that from the IU, only alternate address space accesses with ASI[7:4]
containing 0, 2 or 4 ones may be used (ASI[7:4] = 0000, 0011, 0101, 0110, 1001, 1010,
1100 or 1111), otherwise an ASI and SIZE parity error will be detected in the MEC, as
the IU computes ASPAR over the full ASI[7:0] range.
D[31:0] - Data Bus (bi-directional)
These pins form a 32-bit bi-directional data bus that serves as the interface between the
IU and the MEC. It is driven by the MEC only during read of its internal registers, when
reading the boot PROM in 8-bit mode, and when a single bit error is detected by the
EDAC. When implementing a system with an 8-bit PROM, the PROM shall be
connected to bits D[7:0]. In case of Direct Memory Access, DMA, it is driven or read by
the DMA unit.
DPARIO - Data Bus Parity Input/Output (bi-directional)
This pin is used by the MEC to check and generate the odd parity over the 32-bit data
bus during write cycles. A DMA unit must supply this bit in case DMA parity is
enabled. See also Table 4 on page 32.
MATRA MHS
Rev. D (10 Apr. 97)
66