tsc693e ETC-unknow, tsc693e Datasheet - Page 71

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

4.2.2. Memory System Interface Signals
BA[1:0] - Boot PROM Latched Address used for 8-bit Wide PROM (output)
These outputs are used when 8-bit wide PROM is connected to the MEC. During a read
access to the PROM, the BA[1:0] will be asserted four times in order to get the four
bytes needed to generate a 32-bit word. The MEC will assert the BA[1:0] in the
sequence according to Table 7.
Table 7 - BA[1:0] Sequence
BA[1:0] Bits in the 32-bit word
11
10
01
00
CB[6:0] - Check Bits (bi-directional)
CB[6:0] is the EDAC checkword over the 33-bit data bus consisting of D[31:0] and the
parity bit (DPARIO). When IU performs a write operation to the main memory, the
MEC will assert the EDAC checkword on the CB[6:0]. During read access from the
main memory, CB[6:0] are input signals and will be used for checking and correction of
the data word and the parity bit. During read access to areas which do not generate a
parity bit, the MEC will latch the data from the accessed address and drive the correct
parity bit on the DPARIO pin.
ALE* - Address Latch Enable (output)
This output is asserted when the address from the IU or a DMA unit is to be latched by
an external latch. The signal is intended to be used to enable the clock input of a flip-
flop used to latch the address from the IU.
PROM8* - Select 8-bit Wide PROM (input)
This input indicates that only 8-bit wide PROM is connected to the MEC. The eight data
lines from the PROM is to be connected to the D[7:0] signals. The MEC will perform a
8-bit to 32-bit conversion when the IU reads from the PROM. There is no EDAC or
parity checking on accesses to the PROM when PROM8 is asserted, and EDAC and
parity bits must be supplied by the PROM when PROM8 is deasserted.
MATRA MHS
Rev. D (10 Apr. 97)
[7:0]
[15:8]
[23:16]
[31:24]
TSC693E
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