tsc693e ETC-unknow, tsc693e Datasheet - Page 47

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

3.18. System Availability
The SYSAV bit in the Error and Reset Status Register (see page 61) can be used by
software to indicate system availability. The SYSAV bit is cleared by reset and is
programmable by software. Note that the SYSAV output of the MEC will be asserted
only if the SYSAV bit is set and SYSERR* is deasserted, i.e. no error has been
detected.
3.19. Test mode and Test Access Port
The MEC includes a number of test facilities such as EDAC test, Parity test, Interrupt
test, Error test and a simple Test Access Port. These test functions are controlled using
the Test Control Register (TCR) (see page 61).
3.19.1. EDAC Test
The EDAC function allows fault injection for memory test purposes and also test of the
EDAC function itself. By enabling EDAC test mode in TCR (ET=1), the bits in the CB
field of TCR will substitute the normal checkbits during store cycles.
3.19.2. Parity Test
The MEC register parity function allows fault injection for parity test purposes. By
enabling parity test mode in TCR (PT=1), wrong parity will be generated when any
MEC register is read.
3.19.3. Interrupt Test
It is possible to test and force interrupts by setting the corresponding bit in the Interrupt
Force Register (page 57). Clearing of interrupts by setting the corresponding bit in the
Interrupt Clear Register (ICR) will always clear the corresponding bit(s) in the
Interrupt Pending Register (IPR), but will never affect the interrupts set in the
Interrupt Force Register (IFR). However, it is possible to remove these interrupts by
clearing the corresponding bit in IFR.
If the MEC is in interrupt test mode the handling of IFR and IPR is different:
When "Interrupt test" is not enabled:
When "Interrupt test" is enabled:
MATRA MHS
Rev. D (10 Apr. 97)
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Setting or clearing a bit in IFR will only affect IFR. The corresponding
interrupt will not be forced.
When the interrupt is acknowledged, the MEC will automatically clear the
bit in the IPR corresponding to the trap address as described above.
Setting a bit in IFR will force the corresponding interrupt if it is not
masked in IMR.
TSC693E
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