tsc693e ETC-unknow, tsc693e Datasheet - Page 67

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
DMAAS - DMA Address Strobe (input)
During DMA transfers (when the external DMA is bus master) this input is used to
inform the MEC that the address from the DMA is valid and that the access cycle shall
start. DMAAS can be asserted multiple times during DMA grant.
DRDY* - Data Ready during DMA access (output)
During DMA read transfers (when the external DMA is bus master) this output is used
to inform the DMA unit that the data are valid. During DMA write transfers this signal
indicates that data have been written into memory.
INULL - Integer Unit Nullify Cycle (input)
INULL is output from the IU to indicate that the current memory access is nullified. See
further the IU signal description.
ExtHOLD* - External unit Hold (input)
This signal input is used to synchronize coprocessor compare instructions with branch
instructions. The MEC shall use this signal for prolonging of ongoing cycle. See further
the FPU FHold / CHold signal description.
ExtCCV - External unit Condition Codes Valid (input)
This signal input is used to hold the MEC when a coprocessor can not continue
execution. The MEC shall use this signal for prolonging of ongoing cycle. See further
the FPU FCCV / CCCV signal description.
DXFER - Data Transfer (input)
DXFER is used to differentiate between the addresses being sent out for instruction
fetches and the addresses of data fetches. DXFER is asserted by the processor during the
address cycles of all bus data transfer cycles, including both cycles of store single and all
three cycles of store double and atomic load-store. DXFER is sent out unlatched and is
latched in the MEC before it is used. A DMA unit must supply this signal during a
DMA session.
MATRA MHS
Rev. D (10 Apr. 97)
67